Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8694937 | Implementing and checking electronic circuits with flexible ramptime limits and tools for performing the same | Alexander Tetelbaum, Rich Laubhan, Bruce E. Zahn | 2014-04-08 |
| 8543951 | Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow | Vishwas M. Rao, James C. Parker | 2013-09-24 |
| 8539423 | Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics | James C. Parker, Vishwas M. Rao | 2013-09-17 |
| 8522179 | System and method for managing timing margin in a hierarchical integrated circuit design process | William R. Griesbach, Vishwas M. Rao | 2013-08-27 |
| 8341573 | Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow | Vishwas M. Rao, James C. Parker | 2012-12-25 |
| 8332792 | Implementing and checking electronic circuits with flexible ramptime limits and tools for performing the same | Alexander Tetelbaum, Rich Laubhan, Bruce E. Zahn | 2012-12-11 |
| 8307324 | Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics | James C. Parker, Vishwas M. Rao | 2012-11-06 |
| 8281266 | Systematic, normalized metric for analyzing and comparing optimization techniques for integrated circuits employing voltage scaling and integrated circuits designed thereby | James C. Parker, Vishwas M. Rao | 2012-10-02 |
| 8024694 | Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics | James C. Parker, Vishwas M. Rao | 2011-09-20 |