Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8806408 | Methods for designing integrated circuits employing voltage scaling and integrated circuits designed thereby | James C. Parker, Clayton E. Schneider, Jr., Gregory W. Sheets, Prasad Subbarao | 2014-08-12 |
| 8689161 | Methods for designing integrated circuits employing pre-determined timing-realizable clock-insertion delays and integrated circuit design tools | James C. Parker | 2014-04-01 |
| 8683407 | Hierarchical design flow generator | James C. Parker | 2014-03-25 |
| 8543951 | Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow | Joseph J. Jamann, James C. Parker | 2013-09-24 |
| 8539423 | Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics | Joseph J. Jamann, James C. Parker | 2013-09-17 |
| 8539419 | Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the method | James C. Parker | 2013-09-17 |
| 8522179 | System and method for managing timing margin in a hierarchical integrated circuit design process | William R. Griesbach, Joseph J. Jamann | 2013-08-27 |
| 8468478 | Methods for measurement and prediction of hold-time and exceeding hold time limits due to cells with tied input pins | Stephanie L. Alter, Kevin D. Drucker, Leon Song | 2013-06-18 |
| 8341573 | Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow | Joseph J. Jamann, James C. Parker | 2012-12-25 |
| 8307324 | Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics | Joseph J. Jamann, James C. Parker | 2012-11-06 |
| 8281266 | Systematic, normalized metric for analyzing and comparing optimization techniques for integrated circuits employing voltage scaling and integrated circuits designed thereby | Joseph J. Jamann, James C. Parker | 2012-10-02 |
| 8239805 | Method for designing integrated circuits employing a partitioned hierarchical design flow and an apparatus employing the method | James C. Parker | 2012-08-07 |
| 8127264 | Methods for designing integrated circuits employing context-sensitive and progressive rules and an apparatus employing one of the methods | James C. Parker, Lalita M. Satapathy, Todd M. Tope | 2012-02-28 |
| 8122422 | Establishing benchmarks for analyzing benefits associated with voltage scaling, analyzing the benefits and an apparatus therefor | James C. Parker, Stephen A. Masnica, Robert C. Sibert | 2012-02-21 |
| 8024694 | Systematic benchmarking system and method for standardized data creation, analysis and comparison of semiconductor technology node characteristics | Joseph J. Jamann, James C. Parker | 2011-09-20 |
| 7930674 | Modifying integrated circuit designs to achieve multiple operating frequency targets | James C. Parker | 2011-04-19 |
| 7610568 | Methods and apparatus for making placement sensitive logic modifications | Stephanie L. Alter | 2009-10-27 |
| 7424693 | Methods for measurement and prediction of hold-time and exceeding hold time limits due to cells with tied input pins | Stephanie L. Alter, Kevin D. Drucker, Leon Song | 2008-09-09 |