Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8775995 | Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer | Alexander Tetelbaum | 2014-07-08 |
| 8321826 | Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer | Alexander Tetelbaum | 2012-11-27 |
| 7739639 | Method and apparatus of core timing prediction of core logic in the chip-level implementation process through an over-core window on a chip-level routing layer | Alexander Tetelbaum | 2010-06-15 |
| 7480881 | Method and computer program for static timing analysis with delay de-rating and clock conservatism reduction | Alexander Tetelbaum, Subodh Yashwant Bhike | 2009-01-20 |
| 7062737 | Method of automated repair of crosstalk violations and timing violations in an integrated circuit design | Alexander Tetelbaum | 2006-06-13 |
| 6948142 | Intelligent engine for protection against injected crosstalk delay | Alexander Tetelbaum | 2005-09-20 |
| 6835972 | Bowtie and T-shaped structures of L-shaped mesh implementation | Radoslav Ratchkov, Thomas Antisseril, Hiroshi Ishikawa, Prasad Subbarao, Bo Shen | 2004-12-28 |
| 6810505 | Integrated circuit design flow with capacitive margin | Alexander Tetelbaum, Maad Al-Dabagh, Duc Huynh | 2004-10-26 |
| 6442737 | Method of generating an optimal clock buffer set for minimizing clock skew in balanced clock trees | Alexander Tetelbaum | 2002-08-27 |