Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11907132 | Final cache directory state indication | Jason D. Kohl, Gregory W. Alexander, Timothy C. Bronson, Winston Herring | 2024-02-20 |
| 10248555 | Managing an effective address table in a multi-slice processor | David S. Levitan, Mehul Patel, Albert J. Van Norstrand, Jr. | 2019-04-02 |
| 10241905 | Managing an effective address table in a multi-slice processor | David S. Levitan, Mehul Patel, Albert J. Van Norstrand, Jr. | 2019-03-26 |
| 9934041 | Pattern based branch prediction | Narasimha R. Adiga, Jatin Bhartia, Matthias D. Heizmann | 2018-04-03 |
| 9760462 | Testing optimization of microprocessor table functions | Narasimha R. Adiga, Jatin Bhartia, Matthias D. Heizmann | 2017-09-12 |
| 9733946 | Pattern based branch prediction | Narasimha R. Adiga, Jatin Bhartia, Matthias D. Heizmann | 2017-08-15 |
| 9547495 | Pattern based branch prediction | Narasimha R. Adiga, Jatin Bhartia, Matthias D. Heizmann | 2017-01-17 |
| 9378020 | Asynchronous lookahead hierarchical branch prediction | James J. Bonanno, Ulrich Mayer, Brian R. Prasky | 2016-06-28 |
| 9304883 | Testing optimization of microprocessor table functions | Narasimha R. Adiga, Jatin Bhartia, Matthias D. Heizmann | 2016-04-05 |
| 9298465 | Asynchronous lookahead hierarchical branch prediction | James J. Bonanno, Ulrich Mayer, Brian R. Prasky | 2016-03-29 |
| 8533394 | Controlling simulation of a microprocessor instruction fetch unit through manipulation of instruction addresses | Darin M. Greene, Alan G. Singletary | 2013-09-10 |
| 8478940 | Controlling simulation of a microprocessor instruction fetch unit through manipulation of instruction addresses | Darin M. Greene, Alan G. Singletary | 2013-07-02 |