Issued Patents All Time
Showing 25 most recent of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11977891 | Implicit program order | Douglas C. Burger | 2024-05-07 |
| 11755484 | Instruction block allocation | Jan Gray, Douglas C. Burger | 2023-09-12 |
| 11743353 | System, method, and computer program for providing a content feed to a user related to a registry and a registry event having an event timeline | August Flanagan, Ian Pearce | 2023-08-29 |
| 11726912 | Coupling wide memory interface to wide write back paths | Douglas C. Burger, Gagan Gupta, David T. Harper | 2023-08-15 |
| 11687345 | Out-of-order block-based processors and instruction schedulers using ready state data indexed by instruction position identifiers | Jan Gray | 2023-06-27 |
| 11681531 | Generation and use of memory access instruction order encodings | Douglas C. Burger | 2023-06-20 |
| 11449342 | Hybrid block-based processor and custom function blocks | Jan Gray | 2022-09-20 |
| D953452 | Reformer exercise apparatus | Kit W. Spelman, Harbir Singh | 2022-05-31 |
| 11126433 | Block-based processor core composition register | Douglas C. Burger | 2021-09-21 |
| 11106467 | Incremental scheduler for out-of-order block ISA processors | Jan Gray | 2021-08-31 |
| 11048517 | Decoupled processor instruction window and operand buffer | Douglas C. Burger, Jan Gray | 2021-06-29 |
| 11016770 | Distinct system registers for logical processors | Douglas C. Burger | 2021-05-25 |
| 10963379 | Coupling wide memory interface to wide write back paths | Douglas C. Burger, Gagan Gupta, David T. Harper | 2021-03-30 |
| 10936316 | Dense read encoding for dataflow ISA | Douglas C. Burger | 2021-03-02 |
| 10871967 | Register read/write ordering | Douglas C. Burger | 2020-12-22 |
| 10776115 | Debug support for block-based processor | Douglas C. Burger | 2020-09-15 |
| 10768936 | Block-based processor including topology and control registers to indicate resource sharing and size of logical processor | Douglas C. Burger | 2020-09-08 |
| D887778 | Grill mount | DeLane Robert Smith | 2020-06-23 |
| 10678544 | Initiating instruction block execution using a register access instruction | Douglas C. Burger | 2020-06-09 |
| 10606651 | Free form expression accelerator with thread length-based thread assignment to clustered soft processor cores that share a functional circuit | Douglas C. Burger, Stephen F. Heil, Sitaram V. Lanka, Andrew R. Putnam | 2020-03-31 |
| 10452399 | Broadcast channel architectures for block-based processors | Douglas C. Burger | 2019-10-22 |
| 10445097 | Multimodal targets in a block-based processor | Douglas C. Burger | 2019-10-15 |
| 10409599 | Decoding information about a group of instructions including a size of the group of instructions | Jan Gray, Doug Burger | 2019-09-10 |
| 10409606 | Verifying branch targets | Douglas C. Burger, Jan Gray | 2019-09-10 |
| 10346168 | Decoupled processor instruction window and operand buffer | Douglas C. Burger, Jan Gray | 2019-07-09 |