| 11157407 |
Implementing atomic primitives using cache line locking |
Mayan Moudgill |
2021-10-26 |
| 10719451 |
Variable translation-lookaside buffer (TLB) indexing |
Mayan Moudgill, Lei Wang, Gary J. Nacer, Aaron G. Milbury, Enrique A. Barria +1 more |
2020-07-21 |
| 10514915 |
Computer processor with address register file |
Mayan Moudgill, Gary J. Nacer, C. John Glossner, Paul Hurtley, Murugappan Senthilvelan +1 more |
2019-12-24 |
| 10169039 |
Computer processor that implements pre-translation of virtual addresses |
Mayan Moudgill, Gary J. Nacer, C. John Glossner, Paul Hurtley, Murugappan Senthilvelan +1 more |
2019-01-01 |
| 9940129 |
Computer processor with register direct branches and employing an instruction preload structure |
Mayan Moudgill, Gary J. Nacer, C. John Glossner, Paul Hurtley, Murugappan Senthilvelan +1 more |
2018-04-10 |
| 9792116 |
Computer processor that implements pre-translation of virtual addresses with target registers |
Mayan Moudgill, Gary J. Nacer, C. John Glossner, Paul Hurtley, Murugappan Senthilvelan +1 more |
2017-10-17 |