SP

Sameer D. Parab

IA Intersil Americas: 7 patents #68 of 468Top 15%
ES Elantec Semiconductor: 3 patents #6 of 24Top 25%
Overall (All Time): #513,663 of 4,157,543Top 15%
10
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8946912 Active area bonding compatible high current structures John T. Gasner, Michael D. Church, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick +1 more 2015-02-03
8652960 Active area bonding compatible high current structures John T. Gasner, Michael D. Church, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick +1 more 2014-02-18
8569896 Active area bonding compatible high current structures John T. Gasner, Michael D. Church, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick +1 more 2013-10-29
8274160 Active area bonding compatible high current structures John T. Gasner, Michael D. Church, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick +1 more 2012-09-25
7795130 Active area bonding compatible high current structures John T. Gasner, Michael D. Church, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick +1 more 2010-09-14
7224074 Active area bonding compatible high current structures John T. Gasner, Michael D. Church, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenic +1 more 2007-05-29
7005369 Active area bonding compatible high current structures John T. Gasner, Michael D. Church, Paul E. Bakeman, Jr., David A. Decrosta, Robert Lomenick +1 more 2006-02-28
6617646 Reduced substrate capacitance high performance SOI process 2003-09-09
6403447 Reduced substrate capacitance high performance SOI process 2002-06-11
5846374 Gas agitated liquid etcher Mark A. Salsbery 1998-12-08