Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9003153 | Method of storing blocks of data in a plurality of memory devices in a redundant manner, a memory controller and a memory system | — | 2015-04-07 |
| 8838878 | Method of writing to a NAND memory block based file system with log based buffering | Dongsheng Xing | 2014-09-16 |
| 8726130 | Dynamic buffer management in a NAND memory controller to minimize age related performance degradation due to error correction | — | 2014-05-13 |
| 7724568 | Memory device having read cache | Fong-Long Lin | 2010-05-25 |
| 7039791 | Instruction cache association crossbar switch | Howard G. Sachs | 2006-05-02 |
| 6892293 | VLIW processor and method therefor | Howard G. Sachs | 2005-05-10 |
| 6360313 | Instruction cache associative crossbar switch | Howard G. Sachs | 2002-03-19 |
| 6185668 | Method and apparatus for speculative execution of instructions | — | 2001-02-06 |
| 6047368 | Processor architecture including grouping circuit | — | 2000-04-04 |
| 5924125 | Method and apparatus for parallel access to consecutive TLB entries | — | 1999-07-13 |
| 5903769 | Conditional vector processing | — | 1999-05-11 |
| 5881258 | Hardware compatibility circuit for a new processor architecture | — | 1999-03-09 |
| 5560028 | Software scheduled superscalar computer architecture | Howard G. Sachs | 1996-09-24 |