Issued Patents All Time
Showing 51–75 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10497084 | Efficient sharing and compression expansion of data across processing systems | Abhishek R. Appu, Altug Koker, John C. Weast, Mike B. Macpherson, Dukhwan Kim +5 more | 2019-12-03 |
| 10417734 | Compute optimization mechanism for deep neural networks | Prasoonkumar Surti, Narayan Srinivasa, Feng Chen, Joydeep Ray, Ben J. Ashbaugh +22 more | 2019-09-17 |
| 10417731 | Compute optimization mechanism for deep neural networks | Prasoonkumar Surti, Narayan Srinivasa, Feng Chen, Joydeep Ray, Ben J. Ashbaugh +22 more | 2019-09-17 |
| 10410098 | Compute optimizations for neural networks | Kevin Nealis, Anbang Yao, Xiaoming Chen, Elmoustapha Ould-Ahmed-Vall, Eriko Nurvitadhi +5 more | 2019-09-10 |
| 10409603 | Processors, methods, systems, and instructions to check and store indications of whether memory addresses are in persistent memory | Christos Margiolas | 2019-09-10 |
| 10402177 | Methods and systems to vectorize scalar computer program loops having loop-carried dependences | Jayashankar Bharadwaj, Nalini Vasudevan, Albert Hartono | 2019-09-03 |
| 10372450 | Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate | Victor W. Lee, Daehyun Kim, Tin-Fook Ngai, Jayashankar Bharadwaj, Albert Hartono +1 more | 2019-08-06 |
| 10324768 | Lightweight restricted transactional memory for speculative compiler optimization | Cheng Wang, Youfeng Wu, Albert Hartono, Robert Valentine | 2019-06-18 |
| 10304154 | Coordination and increased utilization of graphics processors during inference | Abhishek R. Appu, Altug Koker, John C. Weast, Mike B. Macpherson, Linda L. Hurd +11 more | 2019-05-28 |
| 10261903 | Extend GPU/CPU coherency to multi-GPU cores | Chandrasekaran Sakthivel, Prasoonkumar Surti, John C. Weast, Justin E. Gottschlich, Abhishek R. Appu +11 more | 2019-04-16 |
| 10248422 | Systems, apparatuses, and methods for snooping persistent memory store addresses | — | 2019-04-02 |
| 10242423 | Compute optimizations for low precision machine learning operations | Elmoustapha Ould-Ahmed-Vall, Anbang Yao, Kevin Nealis, Xiaoming Chen, Altug Koker +11 more | 2019-03-26 |
| 10186011 | Programmable coarse grained and sparse matrix compute hardware with advanced scheduling | Eriko Nurvitadhi, Balaji Vembu, Nicolas C. Galoppo Von Borries, Rajkishore Barik, Tsung-Han Lin +13 more | 2019-01-22 |
| 10025570 | Modifying applications for incremental checkpoints | Christos Margiolas | 2018-07-17 |
| 9921832 | Instruction to reduce elements in a vector register with strided access pattern | Albert Hartono, Jayashankar Bharadwaj, Nalini Vasudevan, Victor W. Lee, Daehyun Kim | 2018-03-20 |
| 9921841 | System and method for executing an instruction to permute a mask | — | 2018-03-20 |
| 9910650 | Method and apparatus for approximating detection of overlaps between memory ranges | Albert Hartono, Nalini Vasudevan, Cheng Wang, Youfeng Wu | 2018-03-06 |
| 9898266 | Loop vectorization methods and apparatus | Nalini Vasudevan, Jayashankar Bharadwaj, Christopher J. Hughes, Milind B. Girkar, Mark J. Charney +4 more | 2018-02-20 |
| 9798541 | Apparatus and method for propagating conditionally evaluated values in SIMD/vector execution using an input mask register | Jayashankar Bharadwaj, Nalini Vasudevan, Victor W. Lee, Daehyun Kim, Albert Hartono | 2017-10-24 |
| 9733913 | Methods and systems to vectorize scalar computer program loops having loop-carried dependences | Jayashankar Bharadwaj, Nalini Vasudevan, Albert Hartono | 2017-08-15 |
| 9720667 | Automatic loop vectorization using hardware transactional memory | Albert Hartono, Youfeng Wu, Nalini Vasudevan, Cheng Wang | 2017-08-01 |
| 9710279 | Method and apparatus for speculative vectorization | Nalini Vasudevan, Cheng Wang, Youfeng Wu, Albert Hartono | 2017-07-18 |
| 9703558 | Systems, apparatuses, and methods for setting an output mask in a destination writemask register from a source write mask register using an input writemask and immediate | Victor W. Lee, Daehyun Kim, Tin-Fook Ngai, Jayashankar Bharadwaj, Albert Hartono +1 more | 2017-07-11 |
| 9690582 | Instruction and logic for cache-based speculative vectorization | Nalini Vasudevan, Youfeng Wu, Cheng Wang, Albert Hartono | 2017-06-27 |
| 9690360 | Technologies for discontinuous execution by energy harvesting devices | — | 2017-06-27 |