RR

Raj K. Ramanujan

IN Intel: 69 patents #393 of 30,777Top 2%
DE Digital Equipment: 9 patents #89 of 2,100Top 5%
QU Qualcomm: 4 patents #3,802 of 12,104Top 35%
HP HP: 3 patents #4,446 of 16,619Top 30%
ST Sandisk Technologies: 3 patents #751 of 2,224Top 35%
📍 Federal Way, WA: #3 of 444 inventorsTop 1%
🗺 Washington: #360 of 76,902 inventorsTop 1%
Overall (All Time): #18,502 of 4,157,543Top 1%
88
Patents All Time

Issued Patents All Time

Showing 76–88 of 88 patents

Patent #TitleCo-InventorsDate
8032660 Apparatus and method for managing subscription requests for a network interface component Ravi L. Sahita, David M. Durham, Arun Raghunath, Parthasarathy Sarangam 2011-10-04
7668997 High speed bus system that incorporates uni-directional point-to-point buses James B. Keller, William A. Samaras, John DeRosa, Robert Eugene Stewart 2010-02-23
6928500 High speed bus system that incorporates uni-directional point-to-point buses James B. Keller, William A. Samaras, John DeRosa, Robert Eugene Stewart 2005-08-09
6807609 Interleaving read and write operations on a bus and minimizing buffering on a memory module in a computer system Paul J. Lemmon 2004-10-19
5341491 Apparatus and method for ensuring that lock requests are serviced in a multiprocessor system 1994-08-23
5278974 Method and apparatus for the dynamic adjustment of data transfer timing to equalize the bandwidths of two buses in a computer system having different bandwidths Paul J. Lemmon, Jay C. Stickney 1994-01-11
5263144 Method and apparatus for sharing data between processors in a computer system John H. Zurawski, John De Rosa 1993-11-16
5214770 System for flushing instruction-cache only when instruction-cache address and data-cache address are matched and the execution of a return-from-exception-or-interrupt command Peter J. Bannon, Simon C. Steely, Jr. 1993-05-25
5202973 Method of controlling a shared memory bus in a multiprocessor system for preventing bus collisions and for ensuring a full bus James B. Keller, Jay C. Stickney, Steven Ho, Paul J. Lemmon 1993-04-13
5038278 Cache with at least two fill rates Simon C. Steely, Jr., Peter J. Bannon, Walter A. Beach 1991-08-06
5003459 Cache memory system Simon C. Steely, Jr., Peter J. Bannon, David J. Sager 1991-03-26
4881165 Method and apparatus for high speed data transmission between two systems operating under the same clock with unknown and non constant skew in the clock between the two systems David J. Sager, Anne S. Valiton, Jay C. Stickney 1989-11-14
4825412 Lockout registers David J. Sager, Jeffrey L. Bell 1989-04-25