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USPTO Patent Rankings Data through Dec 31, 2025
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R. Scott Tetrick — 14 Patents

Intel: 14 patents #2,935 of 30,777Top 10%
Portland, OR: #1,308 of 9,213 inventorsTop 15%
Oregon: #3,136 of 28,073 inventorsTop 15%
Overall (All Time): #332,869 of 4,157,543Top 9%
14 Patents All Time
R. Scott Tetrick has been granted 14 US patents while listed as an inventor at Intel. The first was granted in 1997 and the most recent in October 2013. R. Scott Tetrick ranks #332,869 of 4,157,543 US inventors in our database (top 8.0%). Patent records list R. Scott Tetrick in Portland, OR, US.

Patents per Year

Patents granted per year, 1997 to 2013Bar chart with a peak of 4 patents in 2012.peak 41997: 2 patents19971998: 2 patents19982009: 1 patents20092010: 1 patents20102011: 2 patents20112012: 4 patents20122013: 2 patents2013

Issued Patents All Time

Showing 1–14 of 14 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
8572321 Apparatus and method for segmented cache utilization Dale Jeunemann, Oscar P. Pinto 2013-10-29 $22,754,000
8433854 Apparatus and method for cache utilization Dale Juenemann, Jordan Howes, Jeanna N. Matthews, Steven Wells, Glenn J. Hinton +1 more 2013-04-30 $19,607,000
8219757 Apparatus and method for low touch cache management Glenn J. Hinton, Dale Juenemann 2012-07-10 $16,128,000
8214596 Apparatus and method for segmented cache utilization Dale Juenemann, Oscar P. Pinto 2012-07-03 $15,024,000
8166229 Apparatus and method for multi-level cache utilization Dale Juenemann, Robert Brennan 2012-04-24 $30,122,000
8127294 Disk drive for handling conflicting deadlines and methods thereof 2012-02-28 $20,590,000
8051232 Data storage device performance optimization methods and apparatuses Brian Dees, Amber D. Huffman 2011-11-01 $63,216,000
7895397 Using inter-arrival times of data requests to cache data in a computing environment 2011-02-22 $16,036,000
7827352 Loading data from a memory card 2010-11-02 $10,795,000
7539812 System and method to increase DRAM parallelism 2009-05-26 $14,272,000
5768585 System and method for synchronizing multiple processors during power-on self testing Raghu Murthi 1998-06-16 $42,844,000
5737615 Microprocessor power control in a multiprocessor computer system 1998-04-07 $69,264,000
5682512 Use of deferred bus access for address translation in a shared memory clustered computer system 1997-10-28 $146,510,000
5640520 Mechanism for supporting out-of-order service of bus requests with in-order only requesters devices 1997-06-17 $71,790,000