Issued Patents All Time
Showing 51–68 of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8407367 | Unified connector architecture | Ajay V. Bhatt | 2013-03-26 |
| 8087024 | Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cache | Sridhar Lakshmanamurthy, Wilson Liao, Jeen-Yuan Miin, Yim Pun | 2011-12-27 |
| 7991293 | Unified optical connector architecture | — | 2011-08-02 |
| 7929536 | Buffer management for communication protocols | Alok Kumar, Eswar Eduri, Uday Naik | 2011-04-19 |
| 7730501 | Method for parallel processing of events within multiple event contexts maintaining ordered mutual exclusion | Alok Kumar | 2010-06-01 |
| 7684319 | Transmission control protocol congestion window | Alok Kumar, Eswar Eduri, Uday Naik | 2010-03-23 |
| 7577157 | Facilitating transmission of a packet in accordance with a number of transmit buffers to be associated with the packet | Alok Kumar, Uday Naik, Ameya Varde, David Chou | 2009-08-18 |
| 7536692 | Thread-based engine cache partitioning | Sridhar Lakshmanamurthy, Wilson Liao, Jeen-Yuan Miin, Yim Pun | 2009-05-19 |
| 7525958 | Apparatus and method for two-stage packet classification using most specific filter matching and transport level sharing | Alok Kumar, Michael E. Kounavis, Raj Yavatkar, Sridhar Lakshmanamurthy, Chen-Chi Kuo +1 more | 2009-04-28 |
| 7433364 | Method for optimizing queuing performance | Uday Naik, Alok Kumar, Ameya Varde, David Romano | 2008-10-07 |
| 7373475 | Methods for optimizing memory unit usage to maximize packet throughput for multi-processor multi-threaded architectures | Paul Burkley | 2008-05-13 |
| 7336675 | Optimized back-to-back enqueue/dequeue via physical queue parallelism | Uday Naik, Alok Kumar, Ameya Varde | 2008-02-26 |
| 7275145 | Processing element with next and previous neighbor registers for direct data transfer | Sridhar Lakshmanamurthy, Wilson Liao, Jeen-Yuan Miin, Pun Yim, Chen-Chi Kuo +1 more | 2007-09-25 |
| 7248594 | Efficient multi-threaded multi-processor scheduling implementation | Alok Kumar | 2007-07-24 |
| 7213099 | Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches | Chen-Chi Kuo, Sridhar Lakshmanamurthy, Rohit Natarajan, Kin-Yip Liu, James D. Guilford | 2007-05-01 |
| 7210008 | Memory controller for padding and stripping data in response to read and write commands | Sridhar Lakshmanamurthy, Chen-Chi Kuo, Rohit Natarajan, Mark Rosenbluth | 2007-04-24 |
| 7185153 | Packet assembly | Sridhar Lakshmanamurthy, Chen-Chi Kuo, Rohit Natarajan, Mark Rosenbluth | 2007-02-27 |
| 7159051 | Free packet buffer allocation | Uday Naik, Alok Kumar, Ameya Varde | 2007-01-02 |