PD

Peter L. Doyle

IN Intel: 61 patents #466 of 30,777Top 2%
DE Digital Equipment: 4 patents #305 of 2,100Top 15%
📍 Cameron Park, CA: #6 of 449 inventorsTop 2%
🗺 California: #4,767 of 386,348 inventorsTop 2%
Overall (All Time): #31,801 of 4,157,543Top 1%
67
Patents All Time

Issued Patents All Time

Showing 26–50 of 67 patents

Patent #TitleCo-InventorsDate
10572966 Write out stage generated bounding volumes 2020-02-25
10242494 Conditional shader for graphics Prasoonkumar Surti, Karthik Vaidyanathan, Murali Ramadoss, Michael Apodaca, Abhishek Venkatesh +5 more 2019-03-26
10242496 Adaptive sub-patches system, apparatus and method Devan Burke, Subramaniam Maiyuran, Abhishek R. Appu, Joydeep Ray, Elmoustapha Ould-Ahmed-Vall +2 more 2019-03-26
10217270 Scalable geometry processing within a checkerboard multi-GPU configuration Jeffery S. Boles, Arthur Hunter, Altug Koker, Aditya Navale 2019-02-26
10204393 Pre-pass surface analysis to achieve adaptive anti-aliasing modes Abhishek R. Appu, Joydeep Ray, Subramaniam Maiyuran, Devan Burke, Philip R. Laws +2 more 2019-02-12
10152632 Dynamic brightness and resolution control in virtual environments Radhakrishnan Venkataraman, James M. Holland, Sayan Lahiri, Pattabhiraman K, Kamal Sinha +8 more 2018-12-11
10068307 Command processing for graphics tile-based rendering Balaji Vembu, Michael Apodaca, Hema Chand Nalluri, Jeffery S. Boles 2018-09-04
9953395 On-die tessellation distribution 2018-04-24
9824412 Position-only shading pipeline Saurabh Sharma, Subramaniam Maiyuran, Thomas A. Piazza, Kalyan Kumar BHIRAVABHATLA, Paul A. Johnson +7 more 2017-11-21
9741154 Recording the results of visibility tests at the input geometry object granularity Thomas A. Piazza, Bimal Poddar 2017-08-22
9619855 Scalable geometry processing within a checkerboard multi-GPU configuration Jeffery S. Boles, Arthur D. Hunter Jr., Altug Koker, Aditya Navale 2017-04-11
9619859 Techniques for efficient GPU triangle list adjacency detection and handling Thomas A. Piazza 2017-04-11
9600926 Apparatus and method decoupling visibility bins and render tile dimensions for tiled rendering 2017-03-21
9396032 Priority based context preemption Hema Chand Nalluri, Aditya Navale, Murali Ramadoss, Balaji Vembu, Jeffery S. Boles 2016-07-19
9087392 Techniques for efficient GPU triangle list adjacency detection and handling Thomas A. Piazza 2015-07-21
9064336 Multiple texture compositing Kam Leung, Val G. Cook, Wing Hang Wong 2015-06-23
7791601 Efficient object storage for zone rendering 2010-09-07
7348986 Image rendering Aditya Sreenivas 2008-03-25
7298371 Efficient object storage for zone rendering 2007-11-20
7280113 Multiple texture compositing Kam Leung, Val G. Cook, Wing Hang Wong 2007-10-09
7173627 Apparatus, method and system with a graphics-rendering engine having a graphics context manager Aditya Sreenivas 2007-02-06
7164427 Apparatus, method and system with a graphics-rendering engine having a time allocator Aditya Sreenivas 2007-01-16
6995773 Automatic memory management Aditya Sreenivas 2006-02-07
6954208 Depth write disable for rendering Aditya Sreenivas 2005-10-11
6950108 Bandwidth reduction for rendering using vertex data Thomas A. Piazza 2005-09-27