KV

Kersi H. Vakil

IN Intel: 15 patents #2,741 of 30,777Top 9%
Overall (All Time): #324,909 of 4,157,543Top 8%
15
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
8559530 Transmitters providing cycle encoded signals Jerry G. Jex, Jed Griffin, Arnaud J. Forestier, Abhimanyu Kolla 2013-10-15
8149928 Receivers for cycle encoded signals Jed Griffin, Jerry G. Jex, Arnaud J. Forestier, Abhimanyu Kolla 2012-04-03
8098783 Training pattern for a biased clock recovery tracking loop Adarsh Panikkar, Pete D. Vogt 2012-01-17
7720159 Receivers for cycle encoded signals Jed Griffin, Jerry G. Jex, Arnaud J. Forestier, Abhimanyu Kolla 2010-05-18
7656983 Dual clock domain deskew circuit Daniel Klowden, S. Reji Kumar, Adarsh Panikkar, Abhimanyu Kolla 2010-02-02
7466723 Various methods and apparatuses for lane to lane deskewing Adarsh Panikkar 2008-12-16
7369634 Training pattern for a biased clock recovery tracking loop Adarsh Panikkar, Pete D. Vogt 2008-05-06
7308025 Transmitters providing cycle encoded signals Jerry G. Jex, Jed Griffin, Arnaud J. Forestier, Abhimanyu Kolla 2007-12-11
7305023 Receivers for cycle encoded signals Jed Griffin, Jerry G. Jex, Arnaud J. Forestier, Abhimanyu Kolla 2007-12-04
7050507 Adaptive throughput pulse width modulation communication scheme Jerry G. Jex, Arnaud J. Forestier, Abhimanyu Kolla 2006-05-23
7043392 Interpolator testing system Adarsh Panikkar, Abhimanyu Kolla, Arnaud J. Forestier 2006-05-09
7019550 Leakage testing for differential signal transceiver Eric R. Wehage, Anne Meixner 2006-03-28
7009431 Interpolator linearity testing system Adarsh Panikkar, Abhimanyu Kolla, Arnaud J. Forestier 2006-03-07
6549031 Point to point alternating current (AC) impedance compensation for impedance mismatch Jerry G. Jex, Arnaud J. Forestier, Abhimanyu Kolla 2003-04-15
6466074 Low skew minimized clock splitter William N. Roy, Jerry G. Jex 2002-10-15