Adarsh Panikkar — 9 Patents at Intel

Adarsh Panikkar has been granted 9 US patents while listed as an inventor at Intel. The first was granted in 2006 and the most recent in January 2012. Adarsh Panikkar ranks #535,341 of 4,157,543 US inventors in our database (top 12.9%). Patent records list Adarsh Panikkar in Tacoma, WA, US.

Patents per Year

Issued Patents All Time

Showing 1–9 of 9 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
8098783	Training pattern for a biased clock recovery tracking loop	Kersi H. Vakil, Pete D. Vogt	2012-01-17	$21,678,000
7672335	Non-integer word size translation through rotation of different buffer alignment channels	Wayne C. Ashby, Abhimanyu Kolla	2010-03-02	$14,883,000
7656983	Dual clock domain deskew circuit	Daniel Klowden, S. Reji Kumar, Kersi H. Vakil, Abhimanyu Kolla	2010-02-02	$16,667,000
7500131	Training pattern based de-skew mechanism and frame alignment	S. Reji Kumar, Daniel Klowden, Abhimanyu Kolla	2009-03-03	$13,073,000
7466723	Various methods and apparatuses for lane to lane deskewing	Kersi H. Vakil	2008-12-16	$21,903,000
7369634	Training pattern for a biased clock recovery tracking loop	Kersi H. Vakil, Pete D. Vogt	2008-05-06	$19,899,000
7346795	Delaying lanes in order to align all lanes crossing between two clock domains	Daniel Klowden, S. Reji Kumar	2008-03-18	$17,443,000
7043392	Interpolator testing system	Kersi H. Vakil, Abhimanyu Kolla, Arnaud J. Forestier	2006-05-09	$14,660,000
7009431	Interpolator linearity testing system	Kersi H. Vakil, Abhimanyu Kolla, Arnaud J. Forestier	2006-03-07	$16,275,000

Adarsh Panikkar — 9 Patents

Patents per Year

Issued Patents All Time

Patent Widget