Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11018676 | Coarse delay lock estimation for digital DLL circuits | Khushal Chandan, Dan Shi, Michael J. Allen | 2021-05-25 |
| 10797685 | Jitter cancellation with automatic performance adjustment | Dan Shi, Michael J. Allen | 2020-10-06 |
| 10574241 | Digital phase control with programmable tracking slope having a programmable linear decoder using a coarse code and a fine code to generate delay adjustments to the phase of an input signal | Setul M. Shah, Michael J. Allen, Khushal Chandan | 2020-02-25 |
| 10476488 | Jitter cancellation with automatic performance adjustment | Dan Shi, Michael J. Allen | 2019-11-12 |
| 10270453 | Coarse delay lock estimation for digital DLL circuits | Khushal Chandan, Dan Shi, Michael J. Allen | 2019-04-23 |
| 10164618 | Jitter cancellation with automatic performance adjustment | Dan Shi, Michael J. Allen | 2018-12-25 |
| 10122526 | Phase detector in a delay locked loop | Dan Shi, Michael J. Allen | 2018-11-06 |
| 9805773 | Dual-range clock duty cycle corrector | Dan Shi, Michael J. Allen | 2017-10-31 |
| 9614533 | Digital phase control with programmable tracking slope | Setul M. Shah, Michael J. Allen, Khushal Chandan | 2017-04-04 |
| 9548747 | Glitch-free digitally controlled oscillator code update | Michael J. Allen, Setul M. Shah | 2017-01-17 |
| 9455726 | XOR (exclusive or) based triangular mixing for digital phase control | Michael J. Allen, Khushal Chandan, Setul M. Shah | 2016-09-27 |
| 9407273 | Digital delay-locked loop (DLL) training | Michael J. Allen | 2016-08-02 |
| 9231519 | Temperature compensation for oscillator | Yongping Fan | 2016-01-05 |
| 9166773 | System timing margin improvement of high speed I/O interconnect links by using fine training of phase interpolator | Subratakumar Mandal | 2015-10-20 |
| 9112671 | Gated ring oscillator-based digital eye width monitor for high-speed I/O eye width measurement | Subratakumar Mandal | 2015-08-18 |
| 8929499 | System timing margin improvement of high speed I/O interconnect links by using fine training of phase interpolator | Subratakumar Mandal | 2015-01-06 |
| 8059756 | High-speed serial link receiver with centrally controlled offset cancellation and method | Arif Mahmud | 2011-11-15 |
| 7391824 | High-speed serial link receiver with centrally controlled offset cancellation and method | Arif Mahmud | 2008-06-24 |
| 7249273 | Synchronized serial interface | Chengting Zhao, Ashish Gupta, Edward R. Helder | 2007-07-24 |
| 6831492 | Common-bias and differential structure based DLL | Saeed Abbasi | 2004-12-14 |
| 6614675 | Pipelined content addressable memory with read only element encoding scheme | Carol A. Price | 2003-09-02 |
| 6445329 | High speed analog to digital converter | Saeed Abassi, Michael J. Roden | 2002-09-03 |
| 6301318 | Pipelined phase detector for clock recovery | Tadeusz Kwasniewski | 2001-10-09 |
| 6137735 | Column redundancy circuit with reduced signal path delay | Hirohito Kikukawa, Cynthia Mar | 2000-10-24 |