Issued Patents All Time
Showing 25 most recent of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12386218 | Splicing display device | — | 2025-08-12 |
| 12379738 | Low power hybrid reverse bandgap reference and digital temperature sensor | You Li, David E. Duarte | 2025-08-05 |
| 12147107 | Splicing display panel and preparation method thereof | Meinan Li | 2024-11-19 |
| 12099268 | Spliced display panel and spliced display device | Jun Zhao, Juncheng Xiao | 2024-09-24 |
| 12087186 | Spliced screen of display and display device comprising the same | — | 2024-09-10 |
| 12066705 | Display unit, splicing screen, and display device | — | 2024-08-20 |
| 12061493 | Low power hybrid reverse bandgap reference and digital temperature sensor | You Li, David E. Duarte | 2024-08-13 |
| 12025873 | Spliced panel | Feng Zheng | 2024-07-02 |
| 11841569 | Splicing display device | — | 2023-12-12 |
| 11239794 | Coupled frequency doubler with frequency tracking loop | Dongseok Shin, Hyung Seok Kim | 2022-02-01 |
| 10700688 | Low power and low jitter phase locked loop with digital leakage compensation | Dan Zhang, Bo Xiang | 2020-06-30 |
| 10574243 | Apparatus and method for generating stable reference current | Kuan-Yueh Shen | 2020-02-25 |
| 9768788 | Phase-locked loop with lower power charge pump | Gennady Goltman, Kuan-Yueh Shen | 2017-09-19 |
| 9379717 | Apparatus to reduce power of a charge pump | Gennady Goltman, Kuan-Yueh Shen | 2016-06-28 |
| 9344094 | Temperature compensated PLL calibration | Jeffrey W. Waldrip, Jing Li | 2016-05-17 |
| 9281824 | Clock amplitude detection | Gennady Goltman | 2016-03-08 |
| 9231519 | Temperature compensation for oscillator | Fangxing Wei | 2016-01-05 |
| 8901994 | Digitally switched capacitor loop filter | — | 2014-12-02 |
| 8274339 | Automatic frequency control architecture with digital temperature compensation | Jing Li, Ian A. Young | 2012-09-25 |
| 7593496 | Phase interpolator | Ian A. Young | 2009-09-22 |
| 7583151 | VCO amplitude control | Ian A. Young | 2009-09-01 |
| 7501869 | Low power, low phase jitter, and duty cycle error insensitive clock receiver architecture and circuits for source synchronous digital data communication | Ian A. Young | 2009-03-10 |
| 7501904 | Low power and duty cycle error free matched current phase locked loop | Ian A. Young | 2009-03-10 |
| 7471157 | Low power/zero-offset charge pump circuits for DLLs and PLLs | — | 2008-12-30 |
| 7327174 | Fast locking mechanism for delay lock loops and phase lock loops | Ian A. Young | 2008-02-05 |