Issued Patents All Time
Showing 1–3 of 3 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6137735 | Column redundancy circuit with reduced signal path delay | Fangxing Wei, Hirohito Kikukawa | 2000-10-24 |
| 6134153 | Bi-directional data bus scheme with optimized read and write characters | Valerie L. Lines, Xiao Luo, Sampei Miyamoto | 2000-10-17 |
| 5982674 | Bi-directional data bus scheme with optimized read and write characters | Valeria Lines, Xiao Luo, Sampei Miyamoto | 1999-11-09 |