Issued Patents All Time
Showing 51–66 of 66 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5835748 | Method for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file | Doron Orenstein, Ofri Wechsler, Millind Mittal, Andrew F. Glew, Larry M. Mennemeier +6 more | 1998-11-10 |
| 5825921 | Memory transfer apparatus and method useful within a pattern recognition system | — | 1998-10-20 |
| 5822232 | Method for performing box filter | Mike Kelly, Larry M. Mennemeier | 1998-10-13 |
| 5815421 | Method for transposing a two-dimensional array | Alexander Peleg, Larry M. Mennemeier | 1998-09-29 |
| 5793661 | Method and apparatus for performing multiply and accumulate operations on packed data | Larry M. Mennemeier, Tuan Bui, Eiichi Kowashi, Alexander Peleg, Benny Eitan +3 more | 1998-08-11 |
| 5757432 | Manipulating video and audio signals using a processor which supports SIMD instructions | Alexander Peleg, Larry M. Mennemeier | 1998-05-26 |
| 5752001 | Method and apparatus employing Viterbi scoring using SIMD instructions for data recognition | — | 1998-05-12 |
| 5737561 | Method and apparatus for executing an instruction with multiple brancing options in one cycle | — | 1998-04-07 |
| 5721892 | Method and apparatus for performing multiply-subtract operations on packed data | Alexander Peleg, Millind Mittal, Larry M. Mennemeier, Benny Eitan, Wolf Witt +1 more | 1998-02-24 |
| 5717908 | Pattern recognition system using a four address arithmetic logic unit | — | 1998-02-10 |
| 5701508 | Executing different instructions that cause different data type operations to be performed on single logical register file | Andrew F. Glew, Larry M. Mennemeier, Alexander Peleg, David Bistry, Millind Mittal +4 more | 1997-12-23 |
| 5560039 | Apparatus and method for a four address arithmetic unit | — | 1996-09-24 |
| 5485629 | Method and apparatus for executing control flow instructions in a control flow pipeline in parallel with arithmetic instructions being executed in arithmetic pipelines | — | 1996-01-16 |
| 5459798 | System and method of pattern recognition employing a multiprocessing pipelined apparatus with private pattern memory | Delbert D. Bailey | 1995-10-17 |
| 4985831 | Multiprocessor task scheduling system | Jean-Yves Leclerc, Patrick Scaglia | 1991-01-15 |
| 4974155 | Variable delay branch system | Jean-Yves Leclerc, Patrick Scaglia | 1990-11-27 |