Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11848281 | Die stack with reduced warpage | Yong She, Bin Liu, Zhicheng Ding | 2023-12-19 |
| 11652087 | Interposer design in package structures for wire bonding applications | — | 2023-05-16 |
| 11538746 | Vertical bond-wire stacked chip-scale package with application-specific integrated circuit die on stack, and methods of making same | Zhicheng Ding, Yong She, Bin Liu, Li Deng | 2022-12-27 |
| 11081451 | Die stack with reduced warpage | Yong She, Bin Liu, Zhicheng Ding | 2021-08-03 |
| 10991679 | Stair-stacked dice device in a system in package, and methods of making same | Zhicheng Ding, Bin Liu, Yong She, Li Deng | 2021-04-27 |
| 10971478 | Interposer design in package structures for wire bonding applications | — | 2021-04-06 |
| 10930622 | Prepackaged stair-stacked memory module in a chip scale system in package, and methods of making same | Zhicheng Ding, Bin Liu, Yong She, Li Deng | 2021-02-23 |
| 10770434 | Stair-stacked dice device in a system in package, and methods of making same | Zhicheng Ding, Bin Liu, Yong She, Li Deng | 2020-09-08 |
| 10727208 | Prepackaged stair-stacked memory module in a chip scale system in package, and methods of making same | Zhicheng Ding, Bin Liu, Yong She, Li Deng | 2020-07-28 |