Issued Patents All Time
Showing 26–50 of 77 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10217270 | Scalable geometry processing within a checkerboard multi-GPU configuration | Peter L. Doyle, Jeffery S. Boles, Arthur Hunter, Altug Koker | 2019-02-26 |
| 10191759 | Apparatus and method for scheduling graphics processing unit workloads from virtual machines | David J. Cowperthwaite, Murali Ramadoss, Ankur N. Shah, Balaji Vembu, Altug Koker | 2019-01-29 |
| 10078879 | Process synchronization between engines using data in a memory location | Hema Chand Nalluri | 2018-09-18 |
| 9996386 | Mid-thread pre-emption with software assisted context switch | Brian D. Rauchfuss, Naveen Matam, Michael K. Dwyer | 2018-06-12 |
| 9928564 | Efficient hardware mechanism to ensure shared resource data coherency across draw calls | Prasoonkumar Surti, Jeffery S. Boles | 2018-03-27 |
| 9916257 | Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory | Rajesh M. Sankaran, Altug Koker, Philip R. Lantz, Asit K. Mallick, James B. Crossland +2 more | 2018-03-13 |
| 9886934 | Ordering mechanism for offload graphics scheduling | Bryan R. White, Balaji Vembu, Murali Ramadoss, Altug Koker | 2018-02-06 |
| 9817770 | Memory address re-mapping of graphics data | Balaji Vembu, Wishwesh Anil Gandhi | 2017-11-14 |
| 9779473 | Memory mapping for a graphics processing unit | Altug Koker, Balaji Vembu, Murali Ramadoss | 2017-10-03 |
| 9754342 | Method and apparatus for parallel pixel shading | Prasoonkumar Surti | 2017-09-05 |
| 9678795 | Direct ring 3 submission of processing jobs to adjunct processors | Altug Koker, Balaji Vembu, Murali Ramadoss | 2017-06-13 |
| 9659342 | Mid command buffer preemption for graphics workloads | Hema Chand Nalluri, Murali Ramadoss, Jeffery S. Boles | 2017-05-23 |
| 9633230 | Hardware assist for privilege access violation checks | Hema Chand Nalluri, Murali Ramadoss | 2017-04-25 |
| 9626735 | Page management approach to fully utilize hardware caches for tiled rendering | Altug Koker | 2017-04-18 |
| 9626732 | Supporting atomic operations as post-synchronization operations in graphics processing architectures | Hema Chand Nalluri, Altug Koker | 2017-04-18 |
| 9619855 | Scalable geometry processing within a checkerboard multi-GPU configuration | Peter L. Doyle, Jeffery S. Boles, Arthur D. Hunter Jr., Altug Koker | 2017-04-11 |
| 9589159 | Creating secure communication channels between processing elements | Balaji Vembu, Sathyamurthi Sadhasivan | 2017-03-07 |
| 9563466 | Method and apparatus for supporting programmable software context state execution during hardware context restore flow | Hema Chand Nalluri, Jeffery S. Boles, Murali Ramadoss, Lalit K. Saptarshi | 2017-02-07 |
| 9436972 | System coherency in a distributed graphics processor hierarchy | Altug Koker | 2016-09-06 |
| 9396032 | Priority based context preemption | Hema Chand Nalluri, Peter L. Doyle, Murali Ramadoss, Balaji Vembu, Jeffery S. Boles | 2016-07-19 |
| 9390462 | Memory mapping for a graphics processing unit | Altug Koker, Balaji Vembu, Murali Ramadoss | 2016-07-12 |
| 9383813 | Dynamic control of reduced voltage state of graphics controller component of memory controller | Eric C. Samson | 2016-07-05 |
| 9323684 | Dynamic cache and memory allocation for memory subsystems | Altug Koker | 2016-04-26 |
| 9304813 | CPU independent graphics scheduler for performing scheduling operations for graphics hardware | Balaji Vembu, Murali Ramadoss, David I. Standring, Kritika Bala | 2016-04-05 |
| 9268691 | Fast mechanism for accessing 2n±1 interleaved memory system | Saurabh Sharma, Altug Koker | 2016-02-23 |