Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10373942 | Logic layout with reduced area and method of making the same | Mohit Bajaj, Edward J. Nowak, Kota V. R. M. Murali | 2019-08-06 |
| 10374068 | Tunnel field effect transistors | Harald Gossner, Ramgopal Rao | 2019-08-06 |
| 10325824 | Methods, apparatus and system for threshold voltage control in FinFET devices | Mitsuhiro Togo, Xing Zhang, Palanivel Balasubramaniam | 2019-06-18 |
| 9577079 | Tunnel field effect transistors | Harald Gossner, Ramgopal Rao | 2017-02-21 |
| 8921188 | Methods of forming a transistor device on a bulk substrate and the resulting device | — | 2014-12-30 |
| 8878234 | Semiconductor devices | Harald Gossner, Ramgopal Rao, Angada Bangalore Sachid, Ashish Pal | 2014-11-04 |
| 8405121 | Semiconductor devices | Harald Gossner, Ramgopal Rao, Angada Bangalore Sachid, Ashish Pal | 2013-03-26 |