Issued Patents All Time
Showing 26–40 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7373583 | ECC flag for testing on-chip error correction circuit | — | 2008-05-13 |
| 7272070 | Memory access using multiple activated memory cell rows | — | 2007-09-18 |
| 7164613 | Flexible internal address counting method and apparatus | Khaled Fekih-Romdhane, Wolfgang Hokenmaier | 2007-01-16 |
| 7091553 | Top oxide nitride liner integration scheme for vertical DRAM | Ramachandra Divakaruni | 2006-08-15 |
| 6972266 | Top oxide nitride liner integration scheme for vertical DRAM | Ramachandra Divakaruni | 2005-12-06 |
| 6873003 | Nonvolatile memory cell | Daniele Casarotto | 2005-03-29 |
| 6740558 | SiGe vertical gate contact for gate conductor post etch treatment | — | 2004-05-25 |
| 6734059 | Semiconductor device with deep trench isolation and method of manufacturing same | — | 2004-05-11 |
| 6724030 | System and method for back-side contact for trench semiconductor device characterization | — | 2004-04-20 |
| 6673686 | Method of forming a gate electrode contact spacer for a vertical DRAM device | Arnd Scholz | 2004-01-06 |
| 6620677 | Support liner for isolation trench height control in vertical DRAM processing | — | 2003-09-16 |
| 6617213 | Method for achieving high self-aligning vertical gate studs relative to the support isolation level | — | 2003-09-09 |
| 6586300 | Spacer assisted trench top isolation for vertical DRAM's | Arnd Scholz | 2003-07-01 |
| 6573136 | Isolating a vertical gate contact structure | — | 2003-06-03 |
| 5747802 | Automated non-visual method of locating periodically arranged sub-micron objects | Norbert Arnold, Ernest N. Levine, Rainer Weiland | 1998-05-05 |