Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7187602 | Reducing memory failures in integrated circuits | Thomas Roehr, Michael Jacob | 2007-03-06 |
| 7003432 | Method of and system for analyzing cells of a memory device | Thomas Hladschik, Jens Holzhaeuser, Dieter Rathei | 2006-02-21 |
| 6999887 | Memory cell signal window testing apparatus | Norbert Rehm, Hans-Oliver Joachim, Michael Jacob | 2006-02-14 |
| 6963813 | Method and apparatus for fast automated failure classification for semiconductor wafers | Dieter Rathei, Peter Oswald, Thomas Hladschik | 2005-11-08 |
| 6903959 | Sensing of memory integrated circuits | Thomas Roehr, Hans-Oliver Joachim, Norbert Rehm | 2005-06-07 |
| 6885597 | Sensing test circuit | Thomas Roehr, Hans-Oliver Joachim, Michael Jacob, Takashima Daisaburo | 2005-04-26 |
| 6856560 | Redundancy in series grouped memory architecture | Norbert Rehm, Hans-Oliver Joachim, Thomas Roehr | 2005-02-15 |
| 6826099 | 2T2C signal margin test mode using a defined charge and discharge of BL and /BL | Hans-Oliver Joachim, Thomas Roehr | 2004-11-30 |
| 6807084 | FeRAM memory device | Hans-Oliver Joachim | 2004-10-19 |
| 6800890 | Memory architecture with series grouped by cells | Rainer Bruchhaus, Andreas Hilliger | 2004-10-05 |
| 6731529 | Variable capacitances for memory cells within a cell group | Michael Jacob, Norbert Rehm, Daisaburo Takashima | 2004-05-04 |
| 6731554 | 2T2C signal margin test mode using resistive element | Michael Jacob, Thomas Roehr, Nobert Rehm | 2004-05-04 |
| 6720598 | Series memory architecture | — | 2004-04-13 |
| 6717431 | Method for semiconductor yield loss calculation | Dieter Rathei, Luis G. Andrade, Robert Petter, Thomas Steven Taylor, Babatunde Ashiru +3 more | 2004-04-06 |
| 6707699 | Historical information storage for integrated circuits | Michael Jacob, Norbert Rehm, Hans-Oliver Joachim | 2004-03-16 |
| 6639824 | Memory architecture | Norbert Rehm, Michael Jacob, Thomas Roehr | 2003-10-28 |
| 6553521 | Method for efficient analysis semiconductor failures | Dieter Rathei, Thomas Giegold | 2003-04-22 |
| 6482716 | Uniform recess depth of recessed resist layers in trench structure | — | 2002-11-19 |