Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6977857 | DRAM and refresh method thereof | Masaya Mori, Shinpei Watanabe | 2005-12-20 |
| 6944076 | Dynamic semiconductor memory device and bit line precharge method therefor | Yutaka Nakamura | 2005-09-13 |
| 6925028 | DRAM with multiple virtual bank architecture for random row access | Kohji Hosokawa, Shinpei Watanabe | 2005-08-02 |
| 6898661 | Search memory, memory search controller, and memory search method | Masaya Mori, Shinpei Watanabe | 2005-05-24 |
| 6876228 | Field programmable gate array | Hisatada Miyatake, Kohji Kitamura | 2005-04-05 |
| 6865136 | Timing circuit and method of changing clock period | Shinpei Watanabe, Masaya Mori | 2005-03-08 |
| 6842361 | Memory cell, memory circuit block, data writing method and data reading method | Hisatada Miyatke, Kohji Kitamura | 2005-01-11 |
| 6826076 | Non-volatile memory device | Hideo Asano, Koji Kitamura, Hisatada Miyatake, Kohki Noda, Hiroshi Umezaki | 2004-11-30 |
| 6819323 | Structure and method for gaining fast access to pixel data to store graphic image data in memory | — | 2004-11-16 |
| 6785154 | MRAM and access method thereof | Hisatada Miyatake, Koji Kitamura, Hideo Asano, Kohki Noda, Hiroshi Umezaki | 2004-08-31 |
| 6754134 | Semiconductor storage device having multiple interrupt feature for continuous burst read and write operation | — | 2004-06-22 |
| 6661732 | Memory system having reduced powder data refresh | — | 2003-12-09 |
| 6650573 | Data input/output method | Shinpei Watanabe | 2003-11-18 |
| 6639834 | Data register and access method thereof | Hisatada Miyatake, Koji Kitamura, Hideo Asano, Kohki Noda, Hiroshi Umezaki | 2003-10-28 |
| 6545932 | SDRAM and method for data accesses of SDRAM | Shinpei Watanabe | 2003-04-08 |
| 6252794 | DRAM and data access method for DRAM | Shinpei Watanabe | 2001-06-26 |
| 6085300 | DRAM system with simultaneous burst read and write | Shinpei Watanabe | 2000-07-04 |
| 5745424 | Method for transferring data bit for DRAM | Minoru Furuta | 1998-04-28 |
| 5732042 | Dram array with local latches | Koji Hosokawa | 1998-03-24 |
| 5504702 | Dram cell | — | 1996-04-02 |
| 5339274 | Variable bitline precharge voltage sensing technique for DRAM structures | Sang Hoo Dhong, Toshiaki Kirihata, Hyun Jong Shin, Yoichi Taira, Lewis M. Terman | 1994-08-16 |
| 5257232 | Sensing circuit for semiconductor memory with limited bitline voltage swing | Sang Hoo Dhong, Koji Kitamura, Toshiaki Kirihata | 1993-10-26 |