Issued Patents All Time
Showing 26–50 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9996418 | Error-correction encoding and decoding | Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis | 2018-06-12 |
| 9990279 | Page-level health equalization | Charles J. Camp, Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis | 2018-06-05 |
| 9928923 | Estimation of level-thresholds for memory cells | Nikolaos Papandreou, Haris Pozidis | 2018-03-27 |
| 9891988 | Device and method for storing data in a plurality of multi-level cell memory chips | Tobias Blaettler, Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis, Milos Stanisavljevic | 2018-02-13 |
| 9793929 | Data packing for compression-enabled storage systems | Charles J. Camp, Timothy J. Fisher, Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis | 2017-10-17 |
| 9734012 | Data encoding in solid-state storage devices | Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis | 2017-08-15 |
| 9734010 | Data encoding in solid-state storage apparatus | Nikolaos Papandreou, Charalampos Pozidis | 2017-08-15 |
| 9712190 | Data packing for compression-enabled storage systems | Charles J. Camp, Timothy J. Fisher, Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis | 2017-07-18 |
| 9710199 | Non-volatile memory data storage with low read amplification | Nikolas Ioannou, Ioannis Koltsidas, Thomas Parnell, Roman A. Pletka, Charalampos Pozidis +1 more | 2017-07-18 |
| 9672921 | Device and method for storing data in a plurality of multi-level cell memory chips | Tobias Blaettler, Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis, Milos Stanisavljevic | 2017-06-06 |
| 9647694 | Diagonal anti-diagonal memory structure | Tobias Blaettler, Charles J. Camp, Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis | 2017-05-09 |
| 9639462 | Device for selecting a level for at least one read voltage | Charles J. Camp, Evangelos S. Eleftheriou, Thomas Parnell, Nikolaos Papandreou, Charalampos Pozidis +1 more | 2017-05-02 |
| 9633690 | Cycle-slip resilient iterative data storage read channel architecture | Roy D. Cideciyan, Robert A. Hutchins, Sedat Oelcer | 2017-04-25 |
| 9619328 | Read-detection in multi-level cell memory | Nikolaos Papandreou, Charalampos Pozidis | 2017-04-11 |
| 9588702 | Adapting erase cycle parameters to promote endurance of a memory | Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis, Gary A. Tressler | 2017-03-07 |
| 9583184 | Estimation of level-thresholds for memory cells | Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis, Milos Stanisavljevic | 2017-02-28 |
| 9558782 | Partial reverse concatenation for data storage devices using composite codes | Roy D. Cideciyan, Robert A. Hutchins, Sedat Oelcer | 2017-01-31 |
| 9548760 | Tape header format having efficient and robust codeword interleave designation (CWID) protection | Roy D. Cideciyan, Robert A. Hutchins, Keisuke Tanaka | 2017-01-17 |
| 9542265 | Unequal error protection scheme for headerized sub data sets | Roy D. Cideciyan, Robert A. Hutchins, Keisuke Tanaka | 2017-01-10 |
| 9513813 | Determining prefix codes for pseudo-dynamic data compression utilizing clusters formed based on compression ratio | Tobias Blaettler, Nikolaos Papandreou, Thomas Parnell, Charalampos Pozidis | 2016-12-06 |
| 9502138 | Data encoding in solid-state storage apparatus | Nikolaos Papandreou, Charalampos Pozidis | 2016-11-22 |
| 9477540 | Multi-stage codeword detector | Theodore Antonakopoulos, Nikolaos Papandreou, Charalampos Pozidis | 2016-10-25 |
| 9455749 | Combination error and erasure decoding for product codes | Roy D. Cideciyan, Robert A. Hutchins, Keisuke Tanaka | 2016-09-27 |
| 9401176 | Optimum tape layout selection for improved error correction capability | Roy D. Cideciyan, Robert A. Hutchins | 2016-07-26 |
| 9397695 | Generating a code alphabet of symbols to generate codewords for words used with a program | Roy D. Cideciyan, Glen Alan Jaquette | 2016-07-19 |