Issued Patents All Time
Showing 26–50 of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10103234 | Fabricating raised source drain contacts of a CMOS structure | Veeresh V. Deshpande, Vladimir Djara | 2018-10-16 |
| 10037800 | Resistive memory apparatus using variable-resistance channels with high- and low-resistance regions | Veeresh V. Deshpande, Vara Sudananda Prasad Jonnalagadda, Wabe W. Koelmans, Abu Sebastian | 2018-07-31 |
| 9997409 | Fabricating contacts of a CMOS structure | Veeresh V. Deshpande, Vladimir Djara, Pouya Hashemi | 2018-06-12 |
| 9989703 | Semiconductor structure and method for manufacturing a semiconductor structure | Jean Fompeyrine, Jens Hofrichter, Bert Jan Offrein, Mirja Richter | 2018-06-05 |
| 9984929 | Fabricating contacts of a CMOS structure | Veeresh V. Deshpande, Vladimir Djara, Pouya Hashemi | 2018-05-29 |
| 9953125 | Design/technology co-optimization platform for high-mobility channels CMOS technology | Daniele Caimi, Veeresh V. Deshpande, Vladimir Djara, Jean Fompeyrine | 2018-04-24 |
| 9923022 | Array of optoelectronic structures and fabrication thereof | Mattias B. Borg, Veeresh V. Deshpande, Vladimir Djara, Heike E. Riel, Heinz Schmid | 2018-03-20 |
| 9917164 | Fabricating raised source drain contacts of a CMOS structure | Veeresh V. Deshpande, Vladimir Djara | 2018-03-13 |
| 9891112 | Radiation detector | Stefan Abel, Jean Fompeyrine, Bernd W. Gotsmann, Fabian Menges | 2018-02-13 |
| 9881921 | Fabricating a dual gate stack of a CMOS structure | Veeresh V. Deshpande, Vladimir Djara, Jean Fompeyrine | 2018-01-30 |
| 9870953 | System on chip material co-integration | Takashi Ando, Pouya Hashemi, Alexander Reznicek | 2018-01-16 |
| 9864134 | Semiconductor structure and method for manufacturing a semiconductor structure | Jean Fompeyrine, Jens Hofrichter, Bert Jan Offrein, Mirja Richter | 2018-01-09 |
| 9823414 | Method for fabricating a semiconductor device for use in an optical application | Jens Hofrichter, Mirja Richter, Heike E. Riel | 2017-11-21 |
| 9786664 | Fabricating a dual gate stack of a CMOS structure | Veeresh V. Deshpande, Vladimir Djara, Jean Fompeyrine | 2017-10-10 |
| 9748098 | Controlled confined lateral III-V epitaxy | Karthik Balakrishnan, Pouya Hashemi, Alexander Reznicek | 2017-08-29 |
| 9735010 | Fabrication of semiconductor fin structures | Daniele Caimi, Jean Fompeyrine, Emanuele Uccelli | 2017-08-15 |
| 9704757 | Fabrication of semiconductor structures | Daniele Caimi, Veeresh V. Deshpande, Vladimir Djara, Jean Fompeyrine | 2017-07-11 |
| 9673104 | Fabrication of a CMOS structure | Veeresh V. Deshpande, Vladimir Djara, Jean Fompeyrine | 2017-06-06 |
| 9640394 | Method for fabricating a semiconductor structure | Daniele Caimi, Jean Fompeyrine, Emanuele Uccelli | 2017-05-02 |
| 9570169 | Resistive memory device | Veeresh V. Deshpande, Vara Sudananda Prasad Jonnalagadda, Wabe W. Koelmans, Abu Sebastian | 2017-02-14 |
| 9564452 | Fabrication of hybrid semiconductor circuits | Daniele Caimi, Veeresh V. Deshpande, Vladimir Djara, Jean Fompeyrine | 2017-02-07 |
| 9515090 | Method to form dual channel group III-V and Si/Ge FINFET CMOS and integrated circuit fabricated using the method | Daniele Caimi, Jean Fompeyrine, Effendi Leobandung | 2016-12-06 |
| 9513436 | Semiconductor device | Jens Hofrichter, Mirja Richter, Heike E. Riel | 2016-12-06 |
| 9459405 | Method for fabricating a semiconductor device for use in an optical application | Jens Hofrichter, Mirja Richter, Heike E. Riel | 2016-10-04 |
| 9436215 | Touch surface and method of manufacturing same | Benoît Viallet, Laurence Ressier, Jérémie Grisolia, Lionel Songeon, Eric Mouchel La Fosse | 2016-09-06 |