Issued Patents All Time
Showing 126–144 of 144 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6397303 | Data processing system, cache, and method of cache management including an O state for memory-consistent cache lines | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Sanjeev Ghai | 2002-05-28 |
| 6393528 | Optimized cache allocation algorithm for multiple speculative requests | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Leo James Clark, John Steven Dodson, Guy L. Guthrie | 2002-05-21 |
| 6385695 | Method and system for maintaining allocation information on data castout from an upper level cache | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli | 2002-05-07 |
| 6370618 | Method and system for allocating lower level cache entries for data castout from an upper level cache | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli | 2002-04-09 |
| 6360299 | Extended cache state with prefetched stream ID information | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Leo James Clark, John Steven Dodson, Guy L. Guthrie | 2002-03-19 |
| 6356982 | Dynamic mechanism to upgrade o state memory-consistent cache lines | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Sanjeev Ghai | 2002-03-12 |
| 6356980 | Method and system for bypassing cache levels when casting out from an upper level cache | Lakshminarayana B. Arimilli, Ravi Kumar Arimilli | 2002-03-12 |
| 6349368 | High performance mechanism to support O state horizontal cache-to-cache transfers | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Sanjeev Ghai | 2002-02-19 |
| 6345341 | Method of cache management for dynamically disabling O state memory-consistent data | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Sanjeev Ghai | 2002-02-05 |
| 6338116 | Method and apparatus for a data-less write operation within a cache memory hierarchy for a data processing system | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Sanjeev Ghai | 2002-01-08 |
| 6298416 | Method and apparatus for transmitting control signals within a hierarchial cache memory architecture for a data processing system | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Sanjeev Ghai, Praveen S. Reddy | 2001-10-02 |
| 6282615 | Multiprocessor system bus with a data-less castout mechanism | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, Sanjeev Ghai | 2001-08-28 |
| 6275907 | Reservation management in a non-uniform memory access (NUMA) data processing system | Yoanna Baumgartner, Gary Dale Carpenter, Mark E. Dean, Anna Elman, David B. Glasco | 2001-08-14 |
| 6230219 | High performance multichannel DMA controller for a PCI host bridge with a built-in cache | Guy L. Guthrie | 2001-05-08 |
| 6163815 | Dynamic disablement of a transaction ordering in response to an error | Guy L. Guthrie | 2000-12-19 |
| 6101563 | Configuration access system | Guy L. Guthrie, Kenneth Alan Riek | 2000-08-08 |
| 6049841 | Method and apparatus of selecting data transmission channels | Guy L. Guthrie | 2000-04-11 |
| 6003106 | DMA cache control logic | Guy L. Guthrie | 1999-12-14 |
| 5379386 | Micro channel interface controller | Jeffery L. Swarts, Guy L. Guthrie, Denis A. Smetana | 1995-01-03 |