Issued Patents All Time
Showing 201–225 of 264 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8880959 | Transaction diagnostic block | Christian Jacobi, Marcel Mitran, Timothy J. Slegel | 2014-11-04 |
| 8873750 | Instruction for performing a pseudorandom number generate operation | Bernd Nerz, Tamas Visegrady | 2014-10-28 |
| 8862834 | Shared memory translation facility | Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Donald W. Schmidt, Jaya Srikrishnan +2 more | 2014-10-14 |
| 8838943 | Rotate then operate on selected bits facility and instructions therefore | Timothy J. Slegel, Joachim von Buttlar | 2014-09-16 |
| 8806179 | Non-quiescing key setting facility | Christian Jacobi, Chung-Lung K. Shum, Timothy J. Slegel | 2014-08-12 |
| 8751775 | Non-quiescing key setting facility | Christian Jacobi, Chung-Lung K. Shum, Timothy J. Slegel | 2014-06-10 |
| 8707000 | Execution of a perform frame management function instruction | Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Gustav E. Sittmann, III | 2014-04-22 |
| 8688661 | Transactional processing | Christian Jacobi, Timothy J. Slegel | 2014-04-01 |
| 8683176 | Dynamic address translation with translation exception qualifier | Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer | 2014-03-25 |
| 8682877 | Constrained transaction execution | Christian Jacobi, Timothy J. Slegel | 2014-03-25 |
| 8683138 | Instruction for pre-fetching data and releasing cache lines | Timothy J. Slegel | 2014-03-25 |
| 8677098 | Dynamic address translation with fetch protection | Charles W. Gainey, Jr., Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel +1 more | 2014-03-18 |
| 8650337 | Runtime determination of translation formats for adapter functions | David F. Craddock, Thomas A. Gregg, Eric N. Lais, Donald W. Schmidt | 2014-02-11 |
| 8639858 | Resizing address spaces concurrent to accessing the address spaces | David F. Craddock, Thomas A. Gregg, Donald W. Schmidt | 2014-01-28 |
| 8639911 | Load page table entry address instruction execution based on an address translation format control field | Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel, Gustav E. Sittmann, III | 2014-01-28 |
| 8635430 | Translation of input/output addresses to memory addresses | David F. Craddock, Thomas A. Gregg, Eric N. Lais | 2014-01-21 |
| 8631222 | Translation of input/output addresses to memory addresses | David F. Craddock, Thomas A. Gregg, Eric N. Lais | 2014-01-14 |
| 8631216 | Dynamic address translation with change record override | Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy Siegel, Charles F. Webb | 2014-01-14 |
| 8626970 | Controlling access by a configuration to an adapter function | David F. Craddock, Mark S. Farrell, Beth A. Glendening, Thomas A. Gregg | 2014-01-07 |
| 8621180 | Dynamic address translation with translation table entry format control for identifying format of the translation table entry | Lisa C. Heller, Damian L. Osisek, Erwin Pfeffer, Timothy J. Slegel, Charles F. Webb | 2013-12-31 |
| 8615645 | Controlling the selectively setting of operational parameters for an adapter | David F. Craddock, Mark S. Farrell, Beth A. Glendening, Thomas A. Gregg, Gustav E. Sittmann, III +1 more | 2013-12-24 |
| 8583899 | Parsing-enhacement facility | John R. Ehrman | 2013-11-12 |
| 8572357 | Monitoring events and incrementing counters associated therewith absent taking an interrupt | James H. Mulder, Robert R. Rogers, Robert W. Stjohn | 2013-10-29 |
| 8566480 | Load instruction for communicating with adapters | David F. Craddock, Mark S. Farrell, Thomas A. Gregg | 2013-10-22 |
| 8549182 | Store/store block instructions for communicating with adapters | David F. Craddock, Mark S. Farrell, Thomas A. Gregg | 2013-10-01 |