Issued Patents All Time
Showing 51–59 of 59 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7085917 | Multi-pipe dispatch and execution of complex instructions in a superscalar processor | Fadi Y. Busaba, Steven R. Carlough, John G. Rell, Jr., Timothy J. Slegel | 2006-08-01 |
| 7082517 | Superscalar microprocessor having multi-pipe dispatch and execution unit | Fadi Y. Busaba, Klaus J. Getzlaff, Timothy J. Slegel | 2006-07-25 |
| 7010676 | Last iteration loop branch prediction upon counter threshold and resolution upon counter one | Fadi Y. Busaba, Klaus J. Getzlaff, Timothy J. Slegel | 2006-03-07 |
| 6944753 | Fixed point unit pipeline allowing partial instruction execution during the instruction dispatch cycle | Fadi Y. Busaba, Wen H. Li | 2005-09-13 |
| 6829627 | Floating point unit for multiple data architectures | Eric M. Schwarz | 2004-12-07 |
| 6697833 | Floating-point multiplier for de-normalized inputs | Eric M. Schwarz | 2004-02-24 |
| 6049860 | Pipelined floating point stores | Eric M. Schwarz | 2000-04-11 |
| 6044454 | IEEE compliant floating point unit | Eric M. Schwarz, Timothy J. Slegel, David F. McManigal, Mark S. Farrell | 2000-03-28 |
| 5903479 | Method and system for executing denormalized numbers | Eric M. Schwarz, Bruce C. Giamei, Mark A. Check, John S. Liptay | 1999-05-11 |