Issued Patents All Time
Showing 26–50 of 67 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8030971 | High-density logic techniques with reduced-stack multi-gate field effect transistors | Meng-Hsueh Chiang, Keunwoo Kim | 2011-10-04 |
| 7973564 | High load driving device | Chien-Yu Lu | 2011-07-05 |
| 7956669 | High-density low-power data retention power gating with double-gate devices | Koushik K. Das, Keunwoo Kim | 2011-06-07 |
| 7952422 | Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices | Keunwoo Kim, Jente B. Kuang, Hung C. Ngo, Kevin John Nowka | 2011-05-31 |
| 7903450 | Asymmetrical memory cells and memories using the cells | Jae-Joon Kim, Keunwoo Kim | 2011-03-08 |
| 7876131 | Dual gate transistor keeper dynamic logic | Keunwoo Kim, Jente B. Kuang, Kevin John Nowka | 2011-01-25 |
| 7787285 | Independent-gate controlled asymmetrical memory cell and memory using the cell | Jae-Joon Kim, Keunwoo Kim | 2010-08-31 |
| 7782092 | Cascaded pass-gate test circuit with interposed split-output drive devices | Jente B. Kuang, Hung C. Ngo | 2010-08-24 |
| 7742327 | Computer-readable medium encoding a back-gate controlled asymmetrical memory cell and memory using the cell | Jae-Joon Kim, Keunwoo Kim | 2010-06-22 |
| 7673195 | Circuits and methods for characterizing device variation in electronic memory circuits | Jae-Joon Kim, Saibal Mukhopadhyay | 2010-03-02 |
| 7642864 | Circuits and design structures for monitoring NBTI (negative bias temperature instability) effect and/or PBTI (positive bias temperature instability) effect | Jae-Joon Kim, Tae H. Kim, Pong-Fei Lu, Saibal Mukhopadhyay, Rahul M. Rao +1 more | 2010-01-05 |
| 7548822 | Apparatus and method for determining the slew rate of a signal produced by an integrated circuit | Amlan Ghosh, Jae-Joon Kim, Rahul M. Rao | 2009-06-16 |
| 7492628 | Computer-readable medium encoding a memory using a back-gate controlled asymmetrical memory cell | Jae-Joon Kim, Keunwoo Kim | 2009-02-17 |
| 7417889 | Independent-gate controlled asymmetrical memory cell and memory using the cell | Jae-Joon Kim, Keunwoo Kim | 2008-08-26 |
| 7382162 | High-density logic techniques with reduced-stack multi-gate field effect transistors | Meng-Hsueh Chiang, Keunwoo Kim | 2008-06-03 |
| 7362606 | Asymmetrical memory cells and memories using the cells | Jae-Joon Kim, Keunwoo Kim | 2008-04-22 |
| 7342287 | Power gating schemes in SOI circuits in hybrid SOI-epitaxial CMOS structures | Koushik K. Das, Shih-Hsien Lo, Jeffrey W. Sleight | 2008-03-11 |
| 7336105 | Dual gate transistor keeper dynamic logic | Keunwoo Kim, Jente B. Kuang, Kevin John Nowka | 2008-02-26 |
| 7323908 | Cascaded pass-gate test circuit with interposed split-output drive devices | Jente B. Kuang, Hung C. Ngo | 2008-01-29 |
| 7313012 | Back-gate controlled asymmetrical memory cell and memory using the cell | Jae-Joon Kim, Keunwoo Kim | 2007-12-25 |
| 7298176 | Dual-gate dynamic logic circuit with pre-charge keeper | Hung C. Ngo, Keunwoo Kim, Jente B. Kuang, Kevin John Nowka | 2007-11-20 |
| 7274217 | High performance PFET header in hybrid orientation technology for leakage reduction in digital CMOS VLSI designs | Koushik K. Das, Shih-Hsien Lo | 2007-09-25 |
| 7265589 | Independent gate control logic circuitry | Keunwoo Kim, Jente B. Kuang, Kevin John Nowka | 2007-09-04 |
| 7177177 | Back-gate controlled read SRAM cell | Jae-Joon Kim, Keunwoo Kim | 2007-02-13 |
| 7085798 | Sense-amp based adder with source follower pass gate evaluation tree | Jae-Joon Kim, Rajiv V. Joshi, Kaushik Roy | 2006-08-01 |