Issued Patents All Time
Showing 26–48 of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10546094 | Generating a layout for an integrated circuit | Michael V. Koch, Matthias Ringe | 2020-01-28 |
| 10469063 | Method and apparatus for clock skew control with low jitter in an integrated circuit | Fatih Cilek, Andre Hertwig, Michael V. Koch, Matthias Ringe | 2019-11-05 |
| 10361689 | Static compensation of an active clock edge shift for a duty cycle correction circuit | Fatih Cilek, Michael V. Koch, Matthias Ringe | 2019-07-23 |
| 10355683 | Correcting duty cycle and compensating for active clock edge shift | Michael V. Koch, Matthias Ringe, Fatih Cilek | 2019-07-16 |
| 10348278 | Method and apparatus for clock skew control with low jitter in an integrated circuit | Fatih Cilek, Andre Hertwig, Michael V. Koch, Matthias Ringe | 2019-07-09 |
| 10348279 | Skew control | Fatih Cilek, Michael V. Koch, Matthias Ringe | 2019-07-09 |
| 10326435 | Dynamic control of edge shift for duty cycle correction | Fatih Cilek, Michael V. Koch, Matthias Ringe | 2019-06-18 |
| 10312892 | On-chip waveform measurement | Fatih Cilek, Michael V. Koch, Matthias Ringe | 2019-06-04 |
| 10298217 | Double compression avoidance | Michael V. Koch, Matthias Ringe, Fatih Cilek | 2019-05-21 |
| 10263606 | On-chip waveform measurement | Fatih Cilek, Michael V. Koch, Matthias Ringe | 2019-04-16 |
| 10158351 | Skew control apparatus and algorithm using a low pass filter | Fatih Cilek, Michael V. Koch, Matthias Ringe | 2018-12-18 |
| 10148259 | Skew sensor with enhanced reliability | Fatih Cilek, Michael V. Koch, Matthias Ringe | 2018-12-04 |
| 10110205 | Method and apparatus for clock skew control with low jitter in an integrated circuit | Fatih Cilek, Andre Hertwig, Michael V. Koch, Matthias Ringe | 2018-10-23 |
| 10063222 | Dynamic control of edge shift for duty cycle correction | Fatih Cilek, Michael V. Koch, Matthias Ringe | 2018-08-28 |
| 9953124 | Generating a layout for an integrated circuit | Michael V. Koch, Matthias Ringe | 2018-04-24 |
| 9916409 | Generating a layout for an integrated circuit | Michael V. Koch, Matthias Ringe | 2018-03-13 |
| 9754063 | Reducing dynamic clock skew and/or slew in an electronic circuit | Fatih Cilek, Guenther Hutzl, Michael V. Koch, Matthias Ringe | 2017-09-05 |
| 9306547 | Duty cycle adjustment with error resiliency | Fatih Cilek, Guenther Hutzl, Michael V. Koch, Christian I. Menolfi, Dieter Nissler +1 more | 2016-04-05 |
| 8937494 | Method and apparatus for detecting rising and falling transitions of internal signals of an integrated circuit | Guenther Hutzl, Michael V. Koch, Matthias Ringe | 2015-01-20 |
| 8912824 | Method and apparatus for detecting rising and falling transitions of internal signals of an integrated circuit | Guenther Hutzl, Michael V. Koch, Matthias Ringe | 2014-12-16 |
| 8566771 | Automation of interconnect and routing customization | Florian Braun, Guenther Hutzl, Michael V. Koch, Matthias Ringe | 2013-10-22 |
| 7996808 | Computer readable medium, system and associated method for designing integrated circuits with loop insertions | Jeanne P. Bickford, Markus Buehler, Juergen Koehl, Philipp Salz | 2011-08-09 |
| 7526743 | Method for routing data paths in a semiconductor chip with a plurality of layers | Juergen Koehl, Matthias Ringe | 2009-04-28 |