Issued Patents All Time
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6931473 | Data transfer via Host/PCI-X bridges | Charles S. Graham, Gregory M. Nordstrom, Thomas K. Pokrandt | 2005-08-16 |
| 6925086 | Packet memory system | Michael Curtis | 2005-08-02 |
| 6766405 | Accelerated error detection in a bus bridge circuit | Daniel F. Moertl | 2004-07-20 |
| 6687240 | Transaction routing system | Daniel F. Moertl, Danny Marvin Neal, Steven M. Thurber | 2004-02-03 |
| 6665753 | Performance enhancement implementation through buffer management/bridge settings | Pat Allen Buckland, Michael Anthony Perez, Kiet Tran | 2003-12-16 |
| 6581141 | Toggle for split transaction mode of PCI-X bridge buffer | Richard Allen Kelley, Danny Marvin Neal | 2003-06-17 |
| 6581129 | Intelligent PCI/PCI-X host bridge | Pat Allen Buckland, Daniel F. Moertl, Danny Marvin Neal, Steven M. Thurber, Scott M. Willenborg +1 more | 2003-06-17 |
| 6546447 | Method and apparatus for dynamic PCI combining for PCI bridges | Patrick Allen Buckland, Daniel F. Moertl | 2003-04-08 |
| 6519718 | Method and apparatus implementing error injection for PCI bridges | Charles S. Graham, Kevin Dale Jones, Daniel F. Moertl | 2003-02-11 |
| 6480917 | Device arbitration including peer-to-peer access arbitration | Daniel F. Moertl, Danny Marvin Neal, Steven M. Thurber | 2002-11-12 |
| 6480923 | Information routing for transfer buffers | Daniel F. Moertl, Danny Marvin Neal, Steven M. Thurber | 2002-11-12 |
| 6457077 | System for executing a current information transfer request even when current information transfer request exceeds current available capacity of a transit buffer | Richard Allen Kelley, Danny Marvin Neal, Steven M. Thurber | 2002-09-24 |
| 6425024 | Buffer management for improved PCI-X or PCI bridge performance | Richard Allen Kelley, Danny Marvin Neal, Lawrence D. Whitley | 2002-07-23 |
| 6418503 | Buffer re-ordering system | Daniel F. Moertl, Danny Marvin Neal, Steven M. Thurber | 2002-07-09 |
| 6084934 | Natural throttling of data transfer across asynchronous boundaries | Enrique Q. Garcia, Juan Antonio Yanes | 2000-07-04 |
| 6038620 | Method and system for optimal high speed match in a high performance controller which ensures an input/output interface stays ahead of a host interface | David C. Giese | 2000-03-14 |
| 6038676 | Method and circuit for data integrity verification during DASD data transfer | James Richard Allan Pollock, James Chien-Chiung Chen, David C. Giese | 2000-03-14 |
| 5918242 | General-purpose customizable memory controller | Sudha Sarma | 1999-06-29 |
| 5687393 | System for controlling responses to requests over a data bus between a plurality of master controllers and a slave storage controller by inserting control characters | Lawrence M. Brown, Damon W. Finney, George B. Marenin | 1997-11-11 |
| 5684978 | Synchronous DRAM controller with memory access commands timed for optimized use of data bus | Sudha Sarma | 1997-11-04 |
| 5577236 | Memory controller for reading data from synchronous RAM | Mark C. Johnson, Donald J. Lang, Sudha Sarma, Forrest Lee Wade | 1996-11-19 |
| 5533194 | Hardware-assisted high speed memory test apparatus and method | Donald Jay Albin, Jr., Andrew D. Walls, Kevin G. Zitny | 1996-07-02 |
| 5463752 | Method and system for enhancing the efficiency of communication between multiple direct access storage devices and a storage system controller | Michael T. Benhase, Brent Cameron Beardsley, William G. Sherman | 1995-10-31 |
| 5461720 | System for increasing the efficiency of communications between controller and plurality of host computers by prohibiting retransmission of the same message for predetermined period of time | Brent Cameron Beardsley | 1995-10-24 |
| 5452421 | System for using register sets and state machines sets to communicate between storage controller and devices by using failure condition activity defined in a request | Brent Cameron Beardsley, Michael Porter | 1995-09-19 |