Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5859986 | Bandwidth efficient method and means for resynchronizing a master and slave over a clocked, arbitrated, bidirectional multistate parallel bus using local data recirculation, wait states, and cycle stealing | — | 1999-01-12 |
| 5687393 | System for controlling responses to requests over a data bus between a plurality of master controllers and a slave storage controller by inserting control characters | Lawrence M. Brown, Damon W. Finney, Adalberto G. Yanes | 1997-11-11 |
| 5613067 | Method and apparatus for assuring that multiple messages in a multi-node network are assured fair access to an outgoing data stream | James T. Brady, Damon W. Finney, Donald J. Lang, David R. Nowlen | 1997-03-18 |
| 5195185 | Dynamic bus arbitration with concurrent same bus granting every cycle | — | 1993-03-16 |
| 4378589 | Undirectional looped bus microcomputer architecture | Edward D. Finnegan | 1983-03-29 |
| 4339793 | Function integrated, shared ALU processor apparatus and method | — | 1982-07-13 |
| 4181934 | Microprocessor architecture with integrated interrupts and cycle steals prioritized channel | — | 1980-01-01 |