Issued Patents All Time
Showing 1–25 of 39 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9081901 | Means of control for reconfigurable computers | Lloyd J. Lewins, Kenneth E. Prager, Michael D. Vahey | 2015-07-14 |
| 8278979 | Digital circuits with adaptive resistance to single event upset | — | 2012-10-02 |
| 8040157 | Digital circuits with adaptive resistance to single event upset | — | 2011-10-18 |
| 7795927 | Digital circuits with adaptive resistance to single event upset | — | 2010-09-14 |
| 6948080 | System and method for minimizing upsets in digital microcircuits via ambient radiation monitoring | — | 2005-09-20 |
| 6920545 | Reconfigurable processor with alternately interconnected arithmetic and memory nodes of crossbar switched cluster | Kenneth E. Prager | 2005-07-19 |
| 6775248 | Programmable bandwidth allocation between send and receive in a duplex communication path | Micahel D. Vahey, Kenneth E. Prager, James T. Whitney | 2004-08-10 |
| 6671754 | Techniques for alignment of multiple asynchronous data sources | — | 2003-12-30 |
| 6667519 | Mixed technology microcircuits | Lloyd Frederick Linder, Clifford W. Meyers, Michael D. Vahey | 2003-12-23 |
| 6324664 | Means for testing dynamic integrated circuits | Robert L. Stokes | 2001-11-27 |
| 6038518 | Error correction of system transfer function by use of input compensation | — | 2000-03-14 |
| 5896259 | Preheating device for electronic circuits | Manny Tansavatdi | 1999-04-20 |
| 5870445 | Frequency independent clock synchronizer | — | 1999-02-09 |
| 5731726 | Controllable precision on-chip delay element | Bradley S. Henson | 1998-03-24 |
| 5717702 | Scan testing digital logic with differing frequencies of system clock and test clock | Robert L. Stokes | 1998-02-10 |
| 5708380 | Test for hold time margins in digital systems | — | 1998-01-13 |
| 5703790 | Series connection of multiple digital devices to a single power source | — | 1997-12-30 |
| 5670865 | Circuit to improve the transient response of step-down DC to DC converters | — | 1997-09-23 |
| 5642364 | Contactless testing of inputs and outputs of integrated circuits | — | 1997-06-24 |
| 5606565 | Method of applying boundary test patterns | Christopher L. Edler, Ian Herman, Tuan Hoang, Brian F. Keish, Alida G. Mascitelli | 1997-02-25 |
| 5576645 | Sample and hold flip-flop for CMOS logic | — | 1996-11-19 |
| 5563507 | Method of testing the interconnection between logic devices | — | 1996-10-08 |
| 5528610 | Boundary test cell with self masking capability | Christopher L. Edler, Ian Herman, Tuan Hoang, Brian F. Keish, Alida G. Mascitelli | 1996-06-18 |
| 5488309 | Method of testing the output propagation delay of digital devices | — | 1996-01-30 |
| 5473617 | High impedance technique for testing interconnections in digital systems | — | 1995-12-05 |