Issued Patents All Time
Showing 51–75 of 123 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6362075 | Method for making a diffused back-side layer on a bonded-wafer with a thick bond oxide | Joseph A. Czagas, Dustin A. Woodbury | 2002-03-26 |
| 6184565 | Biasing of island-surrounding material to suppress reduction of breakdown voltage due to field plate acting on buried layer/island junction between high and low impurity concentration regions | — | 2001-02-06 |
| 6051474 | Negative biasing of isolation trench fill to attract mobile positive ions away from bipolar device regions | — | 2000-04-18 |
| 6008512 | Semiconductor device with increased maximum terminal voltage | — | 1999-12-28 |
| 5962908 | Contact regions for narrow trenches in semiconductor devices and method | Dustin A. Woodbury | 1999-10-05 |
| 5929502 | Level shifter stage with punch through diode | — | 1999-07-27 |
| 5929503 | Punch-through diodes and applications | — | 1999-07-27 |
| 5895953 | Ohmic contact to lightly doped islands from a conductive rapid diffusion buried layer | — | 1999-04-20 |
| 5892264 | High frequency analog transistors, method of fabrication and circuit implementation | Christopher K. Davis, George Bajor, Thomas L. Crandell, Taewon Jung, Anthony L. Rivoli | 1999-04-06 |
| 5841169 | Integrated circuit containing devices dielectrically isolated and junction isolated from a substrate | — | 1998-11-24 |
| 5807780 | High frequency analog transistors method of fabrication and circuit implementation | Christopher K. Davis, George Bajor, Thomas L. Crandell, Taewon Jung, Anthony L. Rivoli | 1998-09-15 |
| 5801084 | Bonded wafer processing | Craig J. McLachlan | 1998-09-01 |
| 5780311 | bonded wafer processing | Craig J. McLachlan | 1998-07-14 |
| 5776814 | Process for doping two levels of a double poly bipolar transistor after formation of second poly layer | — | 1998-07-07 |
| 5770880 | P-collector H.V. PMOS switch VT adjusted source/drain | Dustin A. Woodbury, James W. Swonger | 1998-06-23 |
| 5770878 | Trench MOS gate device | — | 1998-06-23 |
| 5744851 | Biasing of island-surrounding material to suppress reduction of breakdown voltage due to field plate acting on buried layer/island junction between high and low impurity concentration regions | — | 1998-04-28 |
| 5686322 | Process for doping two levels of a double poly bipolar transistor after formation of second poly layer | — | 1997-11-11 |
| 5668397 | High frequency analog transistors, method of fabrication and circuit implementation | Christopher K. Davis, George Bajor, Thomas L. Crandell, Taewon Jung, Anthony L. Rivoli | 1997-09-16 |
| 5665634 | Method of increasing maximum terminal voltage of a semiconductor device | — | 1997-09-09 |
| 5652153 | Method of making JFET structures for semiconductor devices with complementary bipolar transistors | — | 1997-07-29 |
| 5650658 | Integration of high voltage lateral MOS devices in low voltage CMOS architecture using CMOS-compatible process steps | — | 1997-07-22 |
| 5643821 | Method for making ohmic contact to lightly doped islands from a silicide buried layer and applications | — | 1997-07-01 |
| 5622878 | Method of making an integration of high voltage lateral MOS devices in low voltage CMOS architecture using CMOS-compatible process steps | — | 1997-04-22 |
| 5622890 | Method of making contact regions for narrow trenches in semiconductor devices | Dustin A. Woodbury | 1997-04-22 |