Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8338914 | Integrated process for thin film resistors with silicides | John T. Gasner, John Stanton, James D. Beasom | 2012-12-25 |
| 7662692 | Integrated process for thin film resistors with silicides | John T. Gasner, John Stanton, James D. Beasom | 2010-02-16 |
| 7605052 | Method of forming an integrated circuit having a device wafer with a diffused doped backside layer | Joseph A. Czagas, James D. Beasom | 2009-10-20 |
| 7341958 | Integrated process for thin film resistors with silicides | John T. Gasner, John Stanton, James D. Beasom | 2008-03-11 |
| 7285475 | Integrated circuit having a device wafer with a diffused doped backside layer | Joseph A. Czagas, James D. Beasom | 2007-10-23 |
| 7187056 | Radiation hardened bipolar junction transistor | Nicolaas W. Van Vonno | 2007-03-06 |
| 7098103 | Method and structure for non-single-polycrystalline capacitor in an integrated circuit | Robert J. Kinzig, James D. Beasom, Timothy Arthur Valade, Donald F. Hemmenway, Kitty Elshot | 2006-08-29 |
| 7029981 | Radiation hardened bipolar junction transistor | Nicolaas W. Van Vonno | 2006-04-18 |
| 6946364 | Integrated circuit having a device wafer with a diffused doped backside layer | Joseph A. Czagas, James D. Beasom | 2005-09-20 |
| 6867495 | Integrated circuit having a device wafer with a diffused doped backside layer | Joseph A. Czagas, James D. Beasom | 2005-03-15 |
| 6667523 | Highly linear integrated resistive contact | Joseph A. Czagas | 2003-12-23 |
| 6551897 | Wafer trench article and process | Patrick A. Begley, Donald F. Hemmenway, George Bajor, Anthony L. Rivoli, Jeanne M. McNamara +1 more | 2003-04-22 |
| 6403472 | Method of forming resistive contacts on intergrated circuits with mobility spoiling ions including high resistive contacts and low resistivity silicide contacts | Joseph A. Czagas | 2002-06-11 |
| 6365953 | Wafer trench article and process | Patrick A. Begley, Donald F. Hemmenway, George Bajor, Anthony L. Rivoli, Jeanne M. McNamara +1 more | 2002-04-02 |
| 6362075 | Method for making a diffused back-side layer on a bonded-wafer with a thick bond oxide | Joseph A. Czagas, James D. Beasom | 2002-03-26 |
| 5962908 | Contact regions for narrow trenches in semiconductor devices and method | James D. Beasom | 1999-10-05 |
| 5933746 | Process of forming trench isolation device | Patrick A. Begley, Donald F. Hemmenway, George Bajor, Anthony L. Rivoli, Jeanne M. McNamara +1 more | 1999-08-03 |
| 5856700 | Semiconductor device with doped semiconductor and dielectric trench sidewall layers | — | 1999-01-05 |
| 5770880 | P-collector H.V. PMOS switch VT adjusted source/drain | James D. Beasom, James W. Swonger | 1998-06-23 |
| 5622890 | Method of making contact regions for narrow trenches in semiconductor devices | James D. Beasom | 1997-04-22 |