Issued Patents All Time
Showing 26–50 of 130 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7006378 | Array architecture and operation methods for a nonvolatile memory | Tomoya Saito, Tomoko Ogura, Kimihiro Satoh | 2006-02-28 |
| 6998658 | Twin NAND device structure, array operations and fabrication method | Tomoko Ogura, Tomoya Saito, Kimihiro Satoh | 2006-02-14 |
| 6982456 | Nonvolatile semiconductor memory device and method for fabricating the same | Nobuyo Sugiyama, Hiromasa Fujimoto, Shinji Odanaka | 2006-01-03 |
| 6900098 | Twin insulator charge storage device operation and its fabrication method | Kimihiro Satoh, Tomoya Saito | 2005-05-31 |
| 6856545 | Fast program to program verify method | Tomoko Ogura, Nori Ogura | 2005-02-15 |
| 6838344 | Simplified twin monos fabrication method with three extra masks to standard CMOS | Kimihiro Satoh, Tomoya Saito | 2005-01-04 |
| 6828621 | Nonvolatile semiconductor memory device and method for fabricating the same | Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka | 2004-12-07 |
| 6825084 | Twin NAND device structure, array operations and fabrication method | Tomoko Ogura, Tomoya Saito, Kimihiro Satoh | 2004-11-30 |
| 6807105 | Fast program to program verify method | Tomoko Ogura, Nori Ogura | 2004-10-19 |
| 6803623 | Nonvolatile semiconductor memory device which can operate at high speed with low voltage, and manufacturing method there | Nobuyo Sugiyama, Shinji Odanaka, Hiromasa Fujimoto | 2004-10-12 |
| 6804149 | Nonvolatile memory cell, operating method of the same and nonvolatile memory array | Yutaka Hayashi | 2004-10-12 |
| 6791139 | Semiconductor memory and method for fabricating the same | Fumihiko Noro | 2004-09-14 |
| 6784040 | Nonvolatile semiconductor memory device and method for fabricating the same | Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka | 2004-08-31 |
| 6770931 | Nonvolatile semiconductor memory device and method for fabricating the same | Nobuyo Sugiyama, Hiromasa Fujimoto, Shinji Odanaka | 2004-08-03 |
| 6759290 | Stitch and select implementation in twin MONOS array | Tomoko Ogura, Tomoya Saito, Kimihiro Satoh | 2004-07-06 |
| 6756271 | Simplified twin monos fabrication method with three extra masks to standard CMOS | Kimihiro Satoh, Tomoya Saito | 2004-06-29 |
| 6714456 | Process for making and programming and operating a dual-bit multi-level ballistic flash memory | Tomoko Ogura | 2004-03-30 |
| 6707079 | Twin MONOS cell fabrication method and array organization | Kumihiro Satoh, Tomoya Saito | 2004-03-16 |
| 6686622 | Semiconductor memory device and manufacturing method thereof | Fumihiko Noro | 2004-02-03 |
| 6686632 | Dual-bit multi-level ballistic MONOS memory | Yutaka Hayashi, Tomoko Ogura | 2004-02-03 |
| 6677203 | Method of manufacturing a semiconductor memory device which reduces the minimum area requirements of the device | Masataka Kusumi | 2004-01-13 |
| 6670240 | Twin NAND device structure, array operations and fabrication method | Tomoko Ogura, Tomoya Saito, Kimihiro Satoh | 2003-12-30 |
| 6642572 | Nonvolatile semiconductor memory device and method for fabricating the same | Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka | 2003-11-04 |
| 6636439 | Fast program to program verify method | Tomoko Ogura, Nori Ogura | 2003-10-21 |
| 6631088 | Twin MONOS array metal bit organization and single cell operation | Tomoya Saito, Tomoko Ogura | 2003-10-07 |