Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9153592 | High density vertical structure nitride flash memory | Seiki Ogura, Tomoko Ogura Iwasaki | 2015-10-06 |
| 9123419 | Complementary reference method for high reliability trap-type non-volatile memory | Tomoko Ogura, Seiki Ogura | 2015-09-01 |
| 8710576 | High density vertical structure nitride flash memory | Seiki Ogura, Tomoko Ogura Iwasaki | 2014-04-29 |
| 8633544 | Twin MONOS array for high speed application | Kimihiro Satoh, Tomoko Ogura, Ki-Tae Park, Yoshitaka Baba | 2014-01-21 |
| 8325542 | Complementary reference method for high reliability trap-type non-volatile memory | Tomoko Ogura, Seiki Ogura | 2012-12-04 |
| 8174885 | High speed operation method for twin MONOS metal bit array | Tomoko Ogura, Seiki Ogura, Tomoya Saito, Yoshitaka Baba | 2012-05-08 |
| 8139410 | Trap-charge non-volatile switch connector for programmable logic | Tomoko Ogura, Seiki Ogura | 2012-03-20 |
| 8089809 | Trap-charge non-volatile switch connector for programmable logic | Tomoko Ogura, Seiki Ogura | 2012-01-03 |
| 8027198 | Trap-charge non-volatile switch connector for programmable logic | Tomoko Ogura, Seiki Ogura | 2011-09-27 |
| 8023326 | Trap-charge non-volatile switch connector for programmable logic | Tomoko Ogura, Seiki Ogura | 2011-09-20 |
| 7936604 | High speed operation method for twin MONOS metal bit array | Tomoko Ogura, Seiki Ogura, Tomoya Saito, Yoshitaka Baba | 2011-05-03 |
| 7742336 | Trap-charge non-volatile switch connector for programmable logic | Tomoko Ogura, Seiki Ogura | 2010-06-22 |
| 7447077 | Referencing scheme for trap memory | Tomoko Ogura, Seiki Ogura, Yoshitaka Baba | 2008-11-04 |
| 7352033 | Twin MONOS array for high speed application | Kimihiro Satoh, Tomoko Ogura, Ki-Tae Park, Yoshitaka Baba | 2008-04-01 |
| 7301820 | Non-volatile memory dynamic operations | Seiki Ogura | 2007-11-27 |
| 7190603 | Nonvolatile memory array organization and usage | Seiki Ogura, Tomoko Ogura, Ki-Tae Park, Kimihiro Satoh, Tomoya Saito | 2007-03-13 |
| 7046553 | Fast program to program verify method | Seiki Ogura, Tomoko Ogura | 2006-05-16 |
| 6856545 | Fast program to program verify method | Seiki Ogura, Tomoko Ogura | 2005-02-15 |
| 6807105 | Fast program to program verify method | Seiki Ogura, Tomoko Ogura | 2004-10-19 |
| 6735118 | CG-WL voltage boosting scheme for twin MONOS | Seki Ogura | 2004-05-11 |
| 6636439 | Fast program to program verify method | Seiki Ogura, Tomoko Ogura | 2003-10-21 |
| 6636438 | Control gate decoder for twin MONOS memory with two bit erase capability | Tomoko Ogura | 2003-10-21 |
| 6631089 | Bit line decoding scheme and circuit for dual bit memory array | Tomoko Ogura | 2003-10-07 |
| 6628546 | Fast program to program verify method | Seiki Ogura, Tomoko Ogura | 2003-09-30 |
| 6628547 | Fast program to program verify method | Seiki Ogura, Tomoko Ogura | 2003-09-30 |