Issued Patents All Time
Showing 1–25 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9123419 | Complementary reference method for high reliability trap-type non-volatile memory | Nori Ogura, Seiki Ogura | 2015-09-01 |
| 8633544 | Twin MONOS array for high speed application | Kimihiro Satoh, Ki-Tae Park, Nori Ogura, Yoshitaka Baba | 2014-01-21 |
| 8325542 | Complementary reference method for high reliability trap-type non-volatile memory | Nori Ogura, Seiki Ogura | 2012-12-04 |
| 8174885 | High speed operation method for twin MONOS metal bit array | Nori Ogura, Seiki Ogura, Tomoya Saito, Yoshitaka Baba | 2012-05-08 |
| 8139410 | Trap-charge non-volatile switch connector for programmable logic | Seiki Ogura, Nori Ogura | 2012-03-20 |
| 8089809 | Trap-charge non-volatile switch connector for programmable logic | Seiki Ogura, Nori Ogura | 2012-01-03 |
| 8027198 | Trap-charge non-volatile switch connector for programmable logic | Seiki Ogura, Nori Ogura | 2011-09-27 |
| 8023326 | Trap-charge non-volatile switch connector for programmable logic | Seiki Ogura, Nori Ogura | 2011-09-20 |
| 7936604 | High speed operation method for twin MONOS metal bit array | Nori Ogura, Seiki Ogura, Tomoya Saito, Yoshitaka Baba | 2011-05-03 |
| 7742336 | Trap-charge non-volatile switch connector for programmable logic | Seiki Ogura, Nori Ogura | 2010-06-22 |
| 7447077 | Referencing scheme for trap memory | Nori Ogura, Seiki Ogura, Yoshitaka Baba | 2008-11-04 |
| 7352033 | Twin MONOS array for high speed application | Kimihiro Satoh, Ki-Tae Park, Nori Ogura, Yoshitaka Baba | 2008-04-01 |
| 7190603 | Nonvolatile memory array organization and usage | Seiki Ogura, Ki-Tae Park, Nori Ogura, Kimihiro Satoh, Tomoya Saito | 2007-03-13 |
| 7149126 | Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory | Seiki Ogura, Yutaka Hayashi | 2006-12-12 |
| 7118961 | Stitch and select implementation in twin MONOS array | Tomoya Saito, Seiki Ogura, Kimihiro Satoh | 2006-10-10 |
| 7046553 | Fast program to program verify method | Seiki Ogura, Nori Ogura | 2006-05-16 |
| 7031192 | Non-volatile semiconductor memory and driving method | Ki-Tae Park | 2006-04-18 |
| 7006378 | Array architecture and operation methods for a nonvolatile memory | Tomoya Saito, Kimihiro Satoh, Seiki Ogura | 2006-02-28 |
| 6998658 | Twin NAND device structure, array operations and fabrication method | Seiki Ogura, Tomoya Saito, Kimihiro Satoh | 2006-02-14 |
| 6999345 | Method of sense and program verify without a reference cell for non-volatile semiconductor memory | Ki-Tae Park | 2006-02-14 |
| 6914791 | High efficiency triple well charge pump circuit | Ki-Tae Park, Shimeno Koji | 2005-07-05 |
| 6856545 | Fast program to program verify method | Seiki Ogura, Nori Ogura | 2005-02-15 |
| 6825084 | Twin NAND device structure, array operations and fabrication method | Seiki Ogura, Tomoya Saito, Kimihiro Satoh | 2004-11-30 |
| 6807105 | Fast program to program verify method | Seiki Ogura, Nori Ogura | 2004-10-19 |
| 6759290 | Stitch and select implementation in twin MONOS array | Tomoya Saito, Seiki Ogura, Kimihiro Satoh | 2004-07-06 |