Issued Patents All Time
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6714456 | Process for making and programming and operating a dual-bit multi-level ballistic flash memory | Seiki Ogura | 2004-03-30 |
| 6686632 | Dual-bit multi-level ballistic MONOS memory | Seiki Ogura, Yutaka Hayashi | 2004-02-03 |
| 6670240 | Twin NAND device structure, array operations and fabrication method | Seiki Ogura, Tomoya Saito, Kimihiro Satoh | 2003-12-30 |
| 6643172 | Bit line decoding scheme and circuit for dual bit memory with a dual bit selection | — | 2003-11-04 |
| 6636439 | Fast program to program verify method | Seiki Ogura, Nori Ogura | 2003-10-21 |
| 6636438 | Control gate decoder for twin MONOS memory with two bit erase capability | Nori Ogura | 2003-10-21 |
| 6631088 | Twin MONOS array metal bit organization and single cell operation | Seiki Ogura, Tomoya Saito | 2003-10-07 |
| 6631089 | Bit line decoding scheme and circuit for dual bit memory array | Nori Ogura | 2003-10-07 |
| 6628546 | Fast program to program verify method | Seiki Ogura, Nori Ogura | 2003-09-30 |
| 6628547 | Fast program to program verify method | Seiki Ogura, Nori Ogura | 2003-09-30 |
| 6611461 | Fast program to program verify method | Seiki Ogura, Nori Ogura | 2003-08-26 |
| 6567314 | Data programming implementation for high efficiency CHE injection | Seiki Ogura | 2003-05-20 |
| 6549463 | Fast program to program verify method | Seiki Ogura, Nori Ogura | 2003-04-15 |
| 6542412 | Process for making and programming and operating a dual-bit multi-level ballistic flash memory | Seiki Ogura | 2003-04-01 |
| 6535430 | Wordline decoder for flash memory | Masaharu Kirihara | 2003-03-18 |
| 6477088 | Usage of word voltage assistance in twin MONOS cell during program and erase | Seiki Ogura, Tomoya Saito | 2002-11-05 |
| 6459622 | Twin MONOS memory cell usage for wide program | Seiki Ogura | 2002-10-01 |
| 6366500 | Process for making and programming and operating a dual-bit multi-level ballistic flash memory | Seiki Ogura | 2002-04-02 |
| 6359807 | Process for making and programming and operating a dual-bit multi-level ballistic flash memory | Seiki Ogura | 2002-03-19 |
| 6248633 | Process for making and programming and operating a dual-bit multi-level ballistic MONOS memory | Seiki Ogura, Yutaba Hayashi | 2001-06-19 |
| 6177318 | Integration method for sidewall split gate monos transistor | Seiki Ogura, Yutaka Hayashi | 2001-01-23 |
| 6133098 | Process for making and programming and operating a dual-bit multi-level ballistic flash memory | Seiki Ogura | 2000-10-17 |
| 6069824 | Semiconductor memory device | Makoto Kojima | 2000-05-30 |
| 6038169 | Read reference scheme for flash memory | Seiki Ogura | 2000-03-14 |
| 6002611 | Fast, low current program with auto-program for flash memory | Seiki Ogura | 1999-12-14 |