Issued Patents All Time
Showing 76–95 of 95 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5659706 | Vector/scalar processor with simultaneous processing and instruction cache filling | Douglas R. Beard, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more | 1997-08-19 |
| 5640524 | Method and apparatus for chaining vector instructions | Douglas R. Beard, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more | 1997-06-17 |
| 5623650 | Method of processing a sequence of conditional vector IF statements | Douglas R. Beard, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more | 1997-04-22 |
| 5598547 | Vector processor having functional unit paths of differing pipeline lengths | Douglas R. Beard, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more | 1997-01-28 |
| 5544337 | Vector processor having registers for control by vector resisters | Douglas R. Beard, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more | 1996-08-06 |
| 5524255 | Method and apparatus for accessing global registers in a multiprocessor system | Douglas R. Beard, George A. Spix, Edward C. Miller, Robert E. Strout, II, Anthony R. Schooler +4 more | 1996-06-04 |
| 5499356 | Method and apparatus for a multiprocessor resource lockout instruction | Roger E. Eckert, Richard E. Hessel, George A. Spix, Jimmie R. Wilson | 1996-03-12 |
| 5430884 | Scalar/vector processor | Douglas R. Beard, Michael A. Woodmansee, Richard G. Blewett, Jeffrey A. Lohman, Alexander A. Silbey +3 more | 1995-07-04 |
| 5381536 | Method and apparatus for separate mark and wait instructions for processors having multiple memory ports | Roger E. Eckert, Richard E. Hessel | 1995-01-10 |
| 5239629 | Dedicated centralized signaling mechanism for selectively signaling devices in a multiprocessor system | Edward C. Miller, George A. Spix, Anthony R. Schooler, Douglas R. Beard, Alexander A. Silbey | 1993-08-24 |
| 5208914 | Method and apparatus for non-sequential resource access | Jimmie R. Wilson, Douglas R. Beard, Steve S. Chen, Roger E. Eckert, Richard E. Hessel +2 more | 1993-05-04 |
| 5193187 | Fast interrupt mechanism for interrupting processors in parallel in a multiprocessor system wherein processors are assigned process ID numbers | Robert E. Strout, II, George A. Spix, Edward C. Miller, Anthony R. Schooler, Alexander A. Silbey +2 more | 1993-03-09 |
| 5175862 | Method and apparatus for a special purpose arithmetic boolean unit | Douglas R. Beard, Michael A. Woodsmansee | 1992-12-29 |
| 5168570 | Method and apparatus for a multiple request toggling priority system | Roger E. Eckert | 1992-12-01 |
| 5165038 | Global registers for a multiprocessor system | Douglas R. Beard, George A. Spix, Edward C. Miller, Robert E. Strout, II, Anthony R. Schooler +4 more | 1992-11-17 |
| 4837730 | Linking scalar results directly to scalar operation inputs on a bidirectional databus in a computer which superpositions vector and scalar operations | Erick M. Cook, Hanan Potash | 1989-06-06 |
| 4760518 | Bi-directional databus system for supporting superposition of vector and scalar operations in a computer | Hanan Potash, Erick M. Cook, Mark A. Haakmeester, Jennifer S. Schuh, William B. Thompson | 1988-07-26 |
| 4538241 | Address translation buffer | Burton L. Levin, Hanan Potash | 1985-08-27 |
| 4532606 | Content addressable memory cell with shift capability | — | 1985-07-30 |
| 4512018 | Shifter circuit | Allen Ta-Ming Wu | 1985-04-16 |