SK

Sasha Kweskin

GC Globalwafers Co.: 10 patents #23 of 221Top 15%
Applied Materials: 3 patents #2,994 of 7,310Top 45%
S( Sunedison Semiconductor Limited (Uen201334164H): 3 patents #9 of 46Top 20%
📍 Chesterfield, MO: #332 of 6,461 inventorsTop 6%
🗺 Missouri: #1,107 of 23,789 inventorsTop 5%
Overall (All Time): #288,878 of 4,157,543Top 7%
16
Patents All Time

Issued Patents All Time

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDate
11984348 Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof 2024-05-14
11848227 Method of manufacturing a semiconductor on insulator structure by a pressurized bond treatment Henry F. Erk 2023-12-19
11114332 Semiconductor on insulator structure comprising a plasma nitride layer and method of manufacture thereof 2021-09-07
10985049 Manufacturing method of smoothing a semiconductor surface Gang Wang, Charles R. Lottes 2021-04-20
10818539 Manufacturing method of smoothing a semiconductor surface Gang Wang, Charles R. Lottes 2020-10-27
10796946 Method of manufacture of a semiconductor on insulator structure Henry F. Erk, Jeffrey L. Libbert, Mayank Bulsara 2020-10-06
10755966 Manufacturing method of smoothing a semiconductor surface Gang Wang, Charles R. Lottes 2020-08-25
10593748 Semiconductor on insulator structure comprising a low temperature flowable oxide layer and method of manufacture thereof 2020-03-17
10573550 Semiconductor on insulator structure comprising a plasma oxide layer and method of manufacture thereof 2020-02-25
10529616 Manufacturing method of smoothing a semiconductor surface Gang Wang, Charles R. Lottes 2020-01-07
10475696 Method of manufacture of a semiconductor on insulator structure Henry F. Erk, Jeffrey L. Libbert, Mayank Bulsara 2019-11-12
10192778 Semiconductor on insulator structure comprising a sacrificial layer and method of manufacture thereof 2019-01-29
10026642 Semiconductor on insulator structure comprising a sacrificial layer and method of manufacture thereof 2018-07-17
8476142 Preferential dielectric gapfill Hiroshi Hamana, Paul Edward Gee, Shankar Venkataraman, Kadar Sapre 2013-07-02
8236708 Reduced pattern loading using bis(diethylamino)silane (C8H22N2Si) as silicon precursor Paul Edward Gee, Shankar Venkataraman, Kedar Sapre 2012-08-07
7994019 Silicon-ozone CVD with reduced pattern loading using incubation period deposition Paul Edward Gee, Shankar Venkataraman, Kedar Sapre 2011-08-09