Issued Patents All Time
Showing 26–38 of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10333497 | Calibration devices for I/O driver circuits having switches biased differently for different temperatures | Anil Kumar, Mahbub Rashed, Sushama Davar | 2019-06-25 |
| 10303196 | On-chip voltage generator for back-biasing field effect transistors in a circuit block | Arif A. Siddiqi, Mahbub Rashed | 2019-05-28 |
| 10199378 | Special construct for continuous non-uniform active region FinFET standard cells | Juhan Kim, Andy T. Nguyen, Mahbub Rashed | 2019-02-05 |
| 10096595 | Antenna diode circuit for manufacturing of semiconductor devices | Juhan Kim, Mahbub Rashed, Anurag Mittal, Sangmoon Kim | 2018-10-09 |
| 10068918 | Contacting SOI subsrates | Christian Haufe, Ingolf Lorenz, Michael Zier, Ulrich Hensel | 2018-09-04 |
| 9893063 | Special construct for continuous non-uniform active region FinFET standard cells | Juhan Kim, Andy T. Nguyen, Mahbub Rashed | 2018-02-13 |
| 9634003 | Special construct for continuous non-uniform RX FinFET standard cells | Juhan Kim, Andy T. Nguyen, Mahbub Rashed | 2017-04-25 |
| 9479179 | Measuring setup and hold times using a virtual delay | Andy T. Nguyen | 2016-10-25 |
| 9337099 | Special constructs for continuous non-uniform active region FinFET standard cells | Juhan Kim, Andy T. Nguyen, Mahbub Rashed | 2016-05-10 |
| 9196548 | Methods of using a trench salicide routing layer | Mahbub Rashed, Srikanth B. Samavedam, David Doman, Subramani Kengeri, Suresh Venkatesan | 2015-11-24 |
| 8966423 | Integrating optimal planar and three-dimensional semiconductor design layouts | Yunfei Deng, Mahbub Rashed, David Doman, Qi Xiang, Jongwook Kye | 2015-02-24 |
| 8904324 | Parameterized cell for planar and finFET technology design | Paul D. Mesa, Qinglei Wang, Qi Xiang, Mahbub Rashed | 2014-12-02 |
| 8689154 | Providing timing-closed FinFET designs from planar designs | Mahbub Rashed, David Doman, Dinesh Somasekhar, Yan Wang, Yunfei Deng +4 more | 2014-04-01 |