AC

Abhishek Choudhury

GR Georgia Tech Research: 1 patents #1,150 of 2,755Top 45%
MP Maxim Integrated Products: 1 patents #560 of 945Top 60%
📍 San Jose, CA: #17,604 of 32,062 inventorsTop 55%
🗺 California: #185,134 of 386,348 inventorsTop 50%
Overall (All Time): #1,929,546 of 4,157,543Top 50%
2
Patents All Time

Issued Patents All Time

Showing 1–2 of 2 patents

Patent #TitleCo-InventorsDate
10204876 Pad defined contact for wafer level package Tiao Zhou, Ricky Agrawal 2019-02-12
8633601 Interconnect assemblies and methods of making and using same Nitesh Kumbhat, Venkatesh Sundaram, Rao R. Tummala 2014-01-21