Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9837299 | Methods of forming 3-D circuits with integrated passive devices | Paul W. Sanders, Robert E. Jones, Michael F. Petras | 2017-12-05 |
| 9698131 | Methods of forming 3-D circuits with integrated passive devices | Paul W. Sanders, Robert E. Jones, Michael F. Petras | 2017-07-04 |
| 9236365 | Methods of forming 3-D circuits with integrated passive devices | Paul W. Sanders, Robert E. Jones, Michael F. Petras | 2016-01-12 |
| 8344503 | 3-D circuits with integrated passive devices | Paul W. Sanders, Robert E. Jones, Michael F. Petras | 2013-01-01 |
| 8329579 | Through substrate VIAS | Paul W. Sanders, Michael F. Petras | 2012-12-11 |
| 8283207 | Methods for forming through-substrate conductor filled vias, and electronic assemblies formed using such methods | Douglas G. Mitchell, Michael F. Petras, Paul W. Sanders | 2012-10-09 |
| 8062975 | Through substrate vias | Paul W. Sanders, Michael F. Petras | 2011-11-22 |
| 7935571 | Through substrate vias for back-side interconnections on very thin semiconductor wafers | Douglas G. Mitchell, Michael F. Petras, Paul W. Sanders | 2011-05-03 |
| 7803714 | Semiconductor through silicon vias of variable size and method of formation | Paul W. Sanders | 2010-09-28 |
| 6345589 | Method and apparatus for forming a borophosphosilicate film | Jeffrey L. Young, Neil L. Pagel | 2002-02-12 |
| 5639687 | Method for forming an integrated circuit pattern on a semiconductor substrate using silicon-rich silicon nitride | Bernard J. Roman, Bich-Yen Nguyen | 1997-06-17 |
| 5539249 | Method and structure for forming an integrated circuit pattern on a semiconductor substrate | Bernard J. Roman, Bich-Yen Nguyen | 1996-07-23 |
| 5378659 | Method and structure for forming an integrated circuit pattern on a semiconductor substrate | Bernard J. Roman, Bich-Yen Nguyen | 1995-01-03 |