Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9831201 | Methods for forming pillar bumps on semiconductor wafers | Guy F. Burgess, Theodore G. Tessier, Lillian C. Thompson | 2017-11-28 |
| 9627254 | Method for building vertical pillar interconnect | Guy F. Burgess, Eugene A. Stout, Theodore G. Tessier, Lillian C. Thompson | 2017-04-18 |
| 9070747 | Electroplating using dielectric bridges | Eugene A. Stout, Douglas M. Scott, Theodore G. Tessier, Guy F. Burgess | 2015-06-30 |
| 8980743 | Method for applying a final metal layer for wafer level packaging and associated device | Guy F. Burgess, Shannon D. Buzard, Douglas M. Scott | 2015-03-17 |
| 8754524 | Wafer-level interconnect for high mechanical reliability applications | Guy F. Burgess, Michael E. Johnson, Ted Tessier, Yuan Lu | 2014-06-17 |
| 8143722 | Wafer-level interconnect for high mechanical reliability applications | Guy F. Burgess, Michael E. Johnson, Ted Tessier, Yuan Lu | 2012-03-27 |
| 8058163 | Enhanced reliability for semiconductor devices using dielectric encasement | John J. Reche, Michael E. Johnson, Guy F. Burgess, Stuart Lichtenthal | 2011-11-15 |