Issued Patents All Time
Showing 51–75 of 76 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7697321 | Non-volatile memory cell and methods thereof | — | 2010-04-13 |
| 7543211 | Toggle memory burst | Joseph J. Nahas, Chitra Subramanian | 2009-06-02 |
| 7532533 | Antifuse circuit and method for selectively programming thereof | Chitra Subramanian | 2009-05-12 |
| 7292484 | Sense amplifier with multiple bits sharing a common reference | Brad J. Garni, Joseph J. Nahas | 2007-11-06 |
| 7224630 | Antifuse circuit | Chitra Subramanian | 2007-05-29 |
| 7206223 | MRAM memory with residual write field reset | Joseph J. Nahas, Chitra Subramanian, Nicholas Rizzo | 2007-04-17 |
| 7154772 | MRAM architecture with electrically isolated read and write circuitry | Joseph J. Nahas, Chitra Subramanian, Bradley J. Garni, Mark Durlam | 2006-12-26 |
| 6909631 | MRAM and methods for reading the MRAM | Mark Durlam, Mark Deherrera, Bradley N. Engel, Bradley J. Garni, Joseph J. Nahas +2 more | 2005-06-21 |
| 6903964 | MRAM architecture with electrically isolated read and write circuitry | Joseph J. Nahas, Chitra Subramanian, Bradley J. Garni, Mark Durlam | 2005-06-07 |
| 6894937 | Accelerated life test of MRAM cells | Bradley J. Garni, Joseph J. Nahas | 2005-05-17 |
| 6888743 | MRAM architecture | Mark Durlam, Brian R. Butcher, Mark Deherrera, Bradley N. Engel, Bradley J. Garni +5 more | 2005-05-03 |
| 6859388 | Circuit for write field disturbance cancellation in an MRAM and method of operation | Joseph J. Nahas, Chitra Subramanian | 2005-02-22 |
| 6842365 | Write driver for a magnetoresistive memory | Joseph J. Nahas, Chitra Subramanian, Halbert S. Lin | 2005-01-11 |
| 6760266 | Sense amplifier and method for performing a read operation in a MRAM | Bradley J. Garni, Mark Deherrera, Mark Durlam, Bradley N. Engel, Joseph J. Nahas +1 more | 2004-07-06 |
| 6744663 | Circuit and method for reading a toggle memory cell | Brad J. Garni, Joseph J. Nahas, Chitra Subramanian | 2004-06-01 |
| 6714440 | Memory architecture with write circuitry and method therefor | Chitra Subramanian, Joseph J. Nahas | 2004-03-30 |
| 6711052 | Memory having a precharge circuit and method therefor | Chitra Subramanian, Joseph J. Nahas | 2004-03-23 |
| 6711068 | Balanced load memory and method of operation | Chitra Subramanian, Brad J. Garni, Joseph J. Nahas, Halbert S. Lin | 2004-03-23 |
| 6700814 | Sense amplifier bias circuit for a memory having at least two distinct resistance states | Joseph J. Nahas, Bradley J. Garni | 2004-03-02 |
| 6693824 | Circuit and method of writing a toggle memory | Joseph J. Nahas, Chitra Subramanian, Brad J. Garni | 2004-02-17 |
| 6667899 | Magnetic memory and method of bi-directional write current programming | Chitra Subramanian, Joseph J. Nahas | 2003-12-23 |
| 6657889 | Memory having write current ramp rate control | Chitra Subramanian, Bradley J. Garni, Halbert S. Lin, Joseph J. Nahas | 2003-12-02 |
| 6621729 | Sense amplifier incorporating a symmetric midpoint reference | Bradley J. Garni, Chitra Subramanian, Joseph J. Nahas | 2003-09-16 |
| 6600690 | Sense amplifier for a memory having at least two distinct resistance states | Joseph J. Nahas, Bradley J. Garni, Chitra Subramanian | 2003-07-29 |
| 6580298 | Three input sense amplifier and method of operation | Chitra Subramanian, Bradley J. Garni, Joseph J. Nahas | 2003-06-17 |