JN

Joseph J. Nahas

FS Freeescale Semiconductor: 15 patents #175 of 3,767Top 5%
Motorola: 15 patents #501 of 12,470Top 5%
AT AT&T: 6 patents #3,053 of 18,772Top 20%
BL Bell Telephone Laboratories: 2 patents #297 of 1,445Top 25%
ET Everspin Technologies: 2 patents #48 of 88Top 55%
UL University Of Notre Dame Du Lac: 2 patents #99 of 437Top 25%
🗺 Texas: #2,381 of 125,132 inventorsTop 2%
Overall (All Time): #76,733 of 4,157,543Top 2%
41
Patents All Time

Issued Patents All Time

Showing 1–25 of 41 patents

Patent #TitleCo-InventorsDate
9825132 Systems and methods for filtering and computation using tunneling transistors Behnam Sedighi, Xiaobo Hu, Michael Niemier 2017-11-21
9362919 Devices for utilizing symFETs for low-power information processing Behnam Sedighi, Michael Niemier, X. Sharon Hu 2016-06-07
8184476 Random access memory architecture including midpoint reference Thomas Andre, Chitra Subramanian 2012-05-22
7543211 Toggle memory burst Thomas Andre, Chitra Subramanian 2009-06-02
7370260 MRAM having error correction code circuitry and method therefor 2008-05-06
7292484 Sense amplifier with multiple bits sharing a common reference Thomas Andre, Brad J. Garni 2007-11-06
7280388 MRAM with a write driver and method therefor 2007-10-09
7266486 Magnetoresistive random access memory simulation 2007-09-04
7206223 MRAM memory with residual write field reset Thomas Andre, Chitra Subramanian, Nicholas Rizzo 2007-04-17
7154772 MRAM architecture with electrically isolated read and write circuitry Thomas Andre, Chitra Subramanian, Bradley J. Garni, Mark Durlam 2006-12-26
7082389 Method and apparatus for simulating a magnetoresistive random access memory (MRAM) 2006-07-25
7012841 Circuit and method for current pulse compensation 2006-03-14
6944052 Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics Chitra Subramanian 2005-09-13
6909631 MRAM and methods for reading the MRAM Mark Durlam, Thomas Andre, Mark Deherrera, Bradley N. Engel, Bradley J. Garni +2 more 2005-06-21
6903964 MRAM architecture with electrically isolated read and write circuitry Thomas Andre, Chitra Subramanian, Bradley J. Garni, Mark Durlam 2005-06-07
6894937 Accelerated life test of MRAM cells Bradley J. Garni, Thomas Andre 2005-05-17
6888743 MRAM architecture Mark Durlam, Thomas Andre, Brian R. Butcher, Mark Deherrera, Bradley N. Engel +5 more 2005-05-03
6859388 Circuit for write field disturbance cancellation in an MRAM and method of operation Thomas Andre, Chitra Subramanian 2005-02-22
6842365 Write driver for a magnetoresistive memory Thomas Andre, Chitra Subramanian, Halbert S. Lin 2005-01-11
6760266 Sense amplifier and method for performing a read operation in a MRAM Bradley J. Garni, Mark Deherrera, Mark Durlam, Bradley N. Engel, Thomas Andre +1 more 2004-07-06
6744663 Circuit and method for reading a toggle memory cell Brad J. Garni, Thomas Andre, Chitra Subramanian 2004-06-01
6714442 MRAM architecture with a grounded write bit line and electrically isolated read bit line 2004-03-30
6714440 Memory architecture with write circuitry and method therefor Chitra Subramanian, Thomas Andre 2004-03-30
6711052 Memory having a precharge circuit and method therefor Chitra Subramanian, Thomas Andre 2004-03-23
6711068 Balanced load memory and method of operation Chitra Subramanian, Brad J. Garni, Halbert S. Lin, Thomas Andre 2004-03-23