Issued Patents All Time
Showing 76–80 of 80 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5553000 | Eliminating retiming bottlenecks to improve performance of synchronous sequential VLSI circuits | Sujit Dey, Steven G. Rothweiler | 1996-09-03 |
| 5550749 | High level circuit design synthesis using transformations | Sujit Dey | 1996-08-27 |
| 5513123 | Non-scan design-for-testability of RT-level data paths | Sujit Dey | 1996-04-30 |
| 5513118 | High level synthesis for partial scan testing | Sujit Dey, Rabindra K. Roy | 1996-04-30 |
| 5502645 | Behavioral synthesis for reconfigurable datapath structures | Lisa Guerra, Jan Rabaey | 1996-03-26 |